XC4VFX12-10FFG668C Xilinx Inc, XC4VFX12-10FFG668C Datasheet - Page 328

• Manufacturer Part Number: XC4VFX12-10FFG668C
• Description: IC FPGA VIRTEX-4 FX 12K 668FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-10FFG668C

• Total Ram Bits: 663552
• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 668-BBGA, FCBGA
• No. Of Logic Blocks: 12312
• No. Of Macrocells: 12312
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1591; XC4VFX12-10FFG668C

Chapter 7: SelectIO Logic Resources
328
IDDR VHDL and Verilog Templates
IDDR VHDL Template
IDDR Verilog Template
The following examples illustrate the instantiation of the IDDR primitive in VHDL and
Verilog.
--Example IDDR component declaration
component IDDR
--Example IDDR instantiation
U_IDDR : IDDR
Port map(
//Example IDDR module declaration
module IDDR (Q1, Q2, C, CE, D, R, S);
generic(
port(
end component;
);
);
);
output Q1;
output Q2;
input C;
input CE;
input D;
tri0 GSR = glbl.GSR;
input R;
input S;
DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
INIT_Q1
INIT_Q2
SRTYPE
Q1
Q2
C
CE
D
R
S
Q1 => user_q1,
Q2 => user_q2,
C => user_c,
CE => user_ce,
D => user_d,
R => user_r,
S => user_s
www.xilinx.com
: out std_ulogic;
: out std_ulogic;
: in
: in
: in
: in
: in
: bit
: bit
: string := "SYNC";
std_ulogic;
std_ulogic;
std_ulogic;
std_ulogic;
std_ulogic
:= '0';
:= '0';
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
R