EP2S30F672C5N Altera, EP2S30F672C5N Datasheet - Page 128
![IC STRATIX II FPGA 30K 672-FBGA](/photos/6/72/67292/544-672-fbga_sml.jpg)
EP2S30F672C5N
Manufacturer Part Number
EP2S30F672C5N
Description
IC STRATIX II FPGA 30K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F672C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
500
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
33880
# I/os (max)
500
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Family Type
Stratix II
No. Of I/o's
500
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Operating Temperature Range
0°C To +85°C
Logic Case Style
BGA
No. Of Pins
672
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1898
EP2S30F672C5N
EP2S30F672C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Document Revision History
Document
Revision History
3–14
Stratix II Device Handbook, Volume 1
May 2007, v4.2 Moved Document Revision History section to the end
Table 3–7. Document Revision History (Part 1 of 2)
Document
Date and
Version
of the chapter.
Updated the
section.
the Device & Pin Options dialog box in the Quartus II software uses a
32-bit CRC circuit to ensure data reliability and is one of the best options
for mitigating SEU.
You can implement the error detection CRC feature with existing circuitry
in Stratix II devices, eliminating the need for external logic. For Stratix II
devices, CRC is computed by the device during configuration and
checked against an automatically computed CRC during normal
operation. The CRC_ERROR pin reports a soft error when configuration
SRAM data is corrupted, triggering device reconfiguration.
Custom-Built Circuitry
Dedicated circuitry is built in the Stratix II devices to perform error
detection automatically. This error detection circuitry in Stratix II devices
constantly checks for errors in the configuration SRAM cells while the
device is in user mode. You can monitor one external pin for the error and
use it to trigger a re-configuration cycle. You can select the desired time
between checks by adjusting a built-in clock divider.
Software Interface
In the Quartus II software version 4.1 and later, you can turn on the
automated error detection CRC feature in the Device & Pin Options
dialog box. This dialog box allows you to enable the feature and set the
internal frequency of the CRC between 400 kHz to 50 MHz. This controls
the rate that the CRC circuitry verifies the internal configuration SRAM
bits in the FPGA device.
For more information on CRC, refer to AN 357: Error Detection Using CRC
in Altera FPGA Devices.
Table 3–7
“Temperature Sensing Diode (TSD)”
Changes Made
shows the revision history for this chapter.
Summary of Changes
—
—
Altera Corporation
May 2007