EP2S30F672C5N Altera, EP2S30F672C5N Datasheet - Page 4
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EP2S30F672C5N
Manufacturer Part Number
EP2S30F672C5N
Description
IC STRATIX II FPGA 30K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F672C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
500
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
33880
# I/os (max)
500
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Family Type
Stratix II
No. Of I/o's
500
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Operating Temperature Range
0°C To +85°C
Logic Case Style
BGA
No. Of Pins
672
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1898
EP2S30F672C5N
EP2S30F672C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Features
1–2
Stratix II Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
ALMs
Adaptive look-up tables (ALUTs)
Equivalent LEs
M512 RAM blocks
M4K RAM blocks
M-RAM blocks
Total RAM bits
DSP blocks
18-bit × 18-bit multipliers
Enhanced PLLs
Fast PLLs
Maximum user I/O pins
Table 1–1. Stratix II FPGA Family Features
One ALM contains two ALUTs. The ALUT is the cell used in the Quartus
This is the equivalent number of LEs in a Stratix device (four-input LUT-based architecture).
These multipliers are implemented using the DSP blocks.
Table
Feature
1–1:
(2)
(3)
■
■
■
■
■
■
■
(1)
Support for numerous single-ended and differential I/O standards
High-speed differential I/O support with DPA circuitry for 1-Gbps
performance
Support for high-speed networking and communications bus
standards including Parallel RapidIO, SPI-4 Phase 2 (POS-PHY
Level 4), HyperTransport™ technology, and SFI-4
Support for high-speed external memory, including DDR and DDR2
SDRAM, RLDRAM II, QDR II SRAM, and SDR SDRAM
Support for multiple intellectual property megafunctions from
Altera MegaCore
Program (AMPP
Support for design security using configuration bitstream
encryption
Support for remote configuration updates
419,328
EP2S15
12,480
15,600
6,240
104
366
78
12
48
0
2
4
1,369,728 2,544,192 4,520,488 6,747,840 9,383,040
EP2S30
13,552
27,104
33,880
SM
202
144
500
®
16
64
1
2
4
functions and Altera Megafunction Partners
) megafunctions
EP2S60
24,176
48,352
60,440
329
255
144
718
36
2
4
8
®
II software for logic synthesis.
EP2S90
36,384
72,768
90,960
488
408
192
902
48
4
4
8
EP2S130
106,032
132,540
53,016
1,126
699
609
252
Altera Corporation
63
6
4
8
EP2S180
143,520
179,400
May 2007
71,760
1,170
930
768
384
96
9
4
8