EP2S30F672C5N Altera, EP2S30F672C5N Datasheet - Page 222

• Manufacturer Part Number: EP2S30F672C5N
• Description: IC STRATIX II FPGA 30K 672-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S30F672C5N

• Number Of Logic Elements/cells: 33880
• Number Of Labs/clbs: 1694
• Total Ram Bits: 1369728
• Number Of I /o: 500
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 33880
• # I/os (max): 500
• Frequency (max): 609.76MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 33880
• Ram Bits: 1369728
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FC-FBGA
• Family Type: Stratix II
• No. Of I/o's: 500
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 672
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1898; EP2S30F672C5N

Duty Cycle Distortion
5–86
Stratix II Device Handbook, Volume 1
Note to
(1)
Notes to
(1)
(2)
LVDS/ HyperTransport
technology
3.3-V LVTTL
3.3-V LVCMOS
2.5V
1.8V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL
LVPECL
Column DDIO Output I/O
Table 5–86. Maximum DCD for DDIO Output on Row I/O Pins with PLL in the
Clock Path (Part 2 of 2)
Table 5–87. Maximum DCD for DDIO Output on Column I/O with PLL in the
Clock Path
Row DDIO Output I/O
The DCD specification is based on a no logic array noise condition.
The DCD specification is based on a no logic array noise condition.
1.2-V HSTL is only supported in -3 devices.
Table
Standard
Standard
Table
5–86:
5–87:
Note (1)
Maximum DCD (PLL Output Clock Feeding
Maximum DCD (PLL Output Clock Feeding
Note (1)
-3 Device
-3 Device
145
100
140
155
180
180
85
85
65
60
50
70
60
60
55
85
DDIO Clock Port)
DDIO Clock Port)
-4 & -5 Device
-4 & -5 Device
160
110
100
155
100
180
95
75
70
65
80
70
70
70
180
Altera Corporation
-
April 2011
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