EP2S30F672I4 Altera, EP2S30F672I4 Datasheet - Page 208

IC STRATIX II FPGA 30K 672-FBGA

EP2S30F672I4

Manufacturer Part Number
EP2S30F672I4
Description
IC STRATIX II FPGA 30K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S30F672I4

Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
500
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
33880
# I/os (max)
500
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1899
EP2S30F672I4

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2S30F672I4
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2S30F672I4
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2S30F672I4
Manufacturer:
ALTERA
0
Part Number:
EP2S30F672I4N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S30F672I4N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2S30F672I4N
Manufacturer:
XILINX
0
Part Number:
EP2S30F672I4N
Manufacturer:
ALTERA
0
Part Number:
EP2S30F672I4N
0
Timing Model
5–72
Stratix II Device Handbook, Volume 1
1.8-V LVTTL
3.3-V LVCMOS
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.2-V HSTL
1.5-V HSTL
Class I
1.8-V HSTL
Class I
1.8-V HSTL
Class II
Differential
SSTL-2 Class I
Differential
SSTL-2 Class II
Differential
SSTL-18 Class I
Differential
SSTL-18 Class II
1.8-V Differential
HSTL Class I
1.8-V Differential
HSTL Class II
1.5-V Differential
HSTL Class I
Table 5–78. Maximum Output Toggle Rate on Stratix II Devices (Part 4 of 5)
I/O Standard
(2)
OCT 50 Ω
OCT 50 Ω
OCT 50 Ω
OCT 50 Ω
OCT 25 Ω
OCT 50 Ω
OCT 25 Ω
OCT 50 Ω
OCT 50 Ω
OCT 50 Ω
OCT 25 Ω
OCT 50 Ω
OCT 25 Ω
OCT 50 Ω
OCT 25 Ω
OCT 50 Ω
OCT 25 Ω
OCT 50 Ω
Strength
Drive
Column I/O Pins (MHz)
700
350
550
600
600
560
550
280
600
650
500
600
600
560
550
650
500
600
-3
550
350
450
500
550
400
500
550
600
500
500
550
400
500
600
500
550
-4
-
450
300
400
500
500
350
450
500
600
450
500
500
350
450
600
450
500
-5
-
700
350
550
600
600
590
600
650
600
600
590
650
600
Row I/O Pins (MHz)
-3
-
-
-
-
-
550
350
450
500
550
400
550
600
500
550
400
600
550
-4
-
-
-
-
-
450
300
400
500
500
350
500
600
500
500
350
600
500
-5
-
-
-
-
-
Note (1)
Clock Outputs (MHz)
700
350
550
600
600
450
550
280
600
650
500
600
600
560
550
650
500
600
-3
Altera Corporation
550
350
450
500
550
400
500
550
600
500
500
550
400
500
600
500
550
-4
-
April 2011
450
300
400
500
500
350
450
500
600
450
500
500
350
450
600
450
500
-5
-

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