EP1AGX90EF1152I6N Altera, EP1AGX90EF1152I6N Datasheet - Page 149

• Manufacturer Part Number: EP1AGX90EF1152I6N
• Description: IC ARRIA GX FPGA 90K 1152FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX90EF1152I6N

• Number Of Logic Elements/cells: 90220
• Number Of Labs/clbs: 4511
• Total Ram Bits: 4477824
• Number Of I /o: 538
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1152-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2387

Chapter 4: DC and Switching Characteristics
I/O Timing Model
I/O Timing Measurement Methodology
© December 2009 Altera Corporation
Different I/O standards require different baseline loading techniques for reporting
timing delays. Altera characterizes timing delays with the required termination for
each I/O standard and with 0 pF (except for PCI and PCI-X which use 10 pF) loading
and the timing is specified up to the output pin of the FPGA device. The Quartus II
software calculates the I/O timing for each I/O standard with a default baseline
loading as specified by the I/O standards.
The following measurements are made during device characterization. Altera
measures clock-to-output delays (t
maximum temperature (PVT) for default loading conditions shown in
Use the following equations to calculate clock pin to output pin timing for Arria GX
devices:
Equation 4–1.
Simulation using IBIS models is required to determine the delays on the PCB traces in
addition to the output pin delay timing reported by the Quartus II software and the
timing model in the device handbook.
1. Simulate the output driver of choice into the generalized test setup, using values
2. Record the time to V
3. Simulate the output driver of choice into the actual PCB trace and load, using the
4. Record the time to V
5. Compare the results of steps
The Quartus II software reports the timing with the conditions shown in
using the above equation.
represented by the output timing of the Quartus II software.
from
appropriate IBIS model or capacitance value to represent the load.
added to or subtracted from the I/O Standard Output Adder delays to yield the
actual worst-case propagation delay (clock-to-output) of the PCB trace.
t
register + IOE output register clock-to-output delay + delay
from output register to output pin + I/O output delay
t
output register + IOE output register clock-to-output delay +
delay from output register to output pin + I/O output delay +
output enable pin delay
CO
xz
Table
/t
from clock pin to I/O pin = delay from clock pad to I/O output
zx
from clock pin to I/O pin = delay from clock pad to I/O
4–44.
MEAS
MEAS
Figure 4–7
.
.
2
and 4. The increase or decrease in delay should be
CO
) at worst-case process, minimum voltage, and
shows the model of the circuit that is
Arria GX Device Handbook, Volume 1
Table
Table 4–44
4–44.
4–27