EP1S80F1020C7 Altera, EP1S80F1020C7 Datasheet - Page 101
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EP1S80F1020C7
Manufacturer Part Number
EP1S80F1020C7
Description
IC STRATIX FPGA 80K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S80F1020C7
Number Of Logic Elements/cells
79040
Number Of Labs/clbs
7904
Total Ram Bits
7427520
Number Of I /o
773
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1440
EP1S80F1020C7
EP1S80F1020C7
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Figure 2–52. Stratix Enhanced PLL
Notes to
(1)
(2)
(3)
(4)
Altera Corporation
July 2005
INCLK0
INCLK1
External feedback is available in PLLs 5 and 6.
This single-ended external output is available from the g0 counter for PLLs 11 and 12.
These four counters and external outputs are available in PLLs 5 and 6.
This connection is only available on EP1S40 and larger Stratix devices. For example, PLLs 5 and 11 are adjacent and
PLLs 6 and 12 are adjacent. The EP1S40 device in the 780-pin FineLine BGA package does not support PLLs 11
and 12.
Figure
Switch-Over
Circuitry
Clock
2–52:
FBIN
/n
(1)
Δt
Enhanced PLLs
Stratix devices contain up to four enhanced PLLs with advanced clock
management features.
Phase Frequency
Detector
PFD
Charge
Pump
VCO Phase Selection
Selectable at Each
PLL Output Port
Lock Detect
& Filter
VCO Phase Selection
Affecting All Outputs
Spectrum
Δt
Spread
Loop
Filter
/m
Figure 2–52
From Adjacent PLL
VCO
8
shows a diagram of the enhanced PLL.
Post-Scale
Counters
/g0
/g1
/g2
/g3
/e0
/e2
/e3
/e1
Stratix Device Handbook, Volume 1
/l0
/l1
Δt
Δt
Δt
Δt
Δt
Δt
Δt
Δt
Δt
Δt
Programmable
Time Delay on
Each PLL Port
4
4
Stratix Architecture
I/O buffers (2)
To I/O buffers or general
routing
Regional
Clocks
Global
Clocks
I/O Buffers (3)
2–87
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