EP1S80F1020C7 Altera, EP1S80F1020C7 Datasheet - Page 45

• Manufacturer Part Number: EP1S80F1020C7
• Description: IC STRATIX FPGA 80K LE 1020-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S80F1020C7

• Number Of Logic Elements/cells: 79040
• Number Of Labs/clbs: 7904
• Total Ram Bits: 7427520
• Number Of I /o: 773
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-1440; EP1S80F1020C7

Altera Corporation
July 2005
Table 2–5. M4K RAM Block Configurations (Simple Dual-Port)
Table 2–6. M4K RAM Block Configurations (True Dual-Port)
Read Port
256
128
256
128
512
512
4K
2K
1K
×
×
×
×
×
×
×
256
256
×
×
512
512
4K
2K
1K
Port A
1
2
4
16
32
18
36
8
9
×
×
×
×
×
×
×
16
18
1
2
4
8
9
4K × 1 2K × 2 1K × 4 512 × 8 256 × 16
v
v
v
v
v
v
4K × 1
v
v
v
v
v
v
The memory address depths and output widths can be configured as
4,096 × 1, 2,048 × 2, 1,024 × 4, 512 × 8 (or 512 × 9 bits), 256 × 16 (or
256 × 18 bits), and 128 × 32 (or 128 × 36 bits). The 128 × 32- or 36-bit
configuration is not available in the true dual-port mode. Mixed-width
configurations are also possible, allowing different read and write
widths.
configurations.
When the M4K RAM block is configured as a shift register block, you can
create a shift register up to 4,608 bits (w × m × n).
v
v
v
v
v
v
v
v
v
v
v
Tables 2–5
2K × 2
v
v
v
v
v
v
v
v
v
v
v
and
1K × 4
v
v
v
v
v
2–6
v
v
v
v
v
v
Write Port
summarize the possible M4K RAM block
512 × 8
Port B
v
v
v
v
v
128 × 32 512 × 9 256 × 18
v
v
v
v
v
v
Stratix Device Handbook, Volume 1
256 × 16
v
v
v
v
v
v
v
v
512 × 9
Stratix Architecture
v
v
v
v
v
256 × 18
128 × 36
v
v
v
v
v
2–31