EP1S80F1020C7 Altera, EP1S80F1020C7 Datasheet - Page 271

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EP1S80F1020C7

Manufacturer Part Number
EP1S80F1020C7
Description
IC STRATIX FPGA 80K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S80F1020C7

Number Of Logic Elements/cells
79040
Number Of Labs/clbs
7904
Total Ram Bits
7427520
Number Of I /o
773
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1440
EP1S80F1020C7

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Altera Corporation
January 2006
t
t
m
l0, l1, g0
t
f
f
f
f
f
t
t
t
t
t
m
l0, l1, g0
JITTER
LOCK
ARESET
IN
INPFD
OUT
OUT_DIFFIO
VCO
INDUTY
INJITTER
DUTY
JITTER
LOCK
Table 4–132. Fast PLL Specifications for -7 Speed Grades (Part 2 of 2)
Table 4–133. Fast PLL Specifications for -8 Speed Grades (Part 1 of 2)
Symbol
Symbol
Period jitter for DIFFIO clock out
Time required for PLL to acquire lock
Multiplication factors for m counter
Multiplication factors for l0, l1, and g0
counter (7),
Minimum pulse width on
signal
CLKIN frequency (1),
Input frequency to PFD
Output frequency for internal global or
regional clock
Output frequency for external clock
driven out on a differential I/O data
channel
VCO operating frequency
CLKIN duty cycle
Period jitter for CLKIN pin
Duty cycle for DFFIO 1× CLKOUT pin
Period jitter for DIFFIO clock out
Time required for PLL to acquire lock
Multiplication factors for m counter
Multiplication factors for l0, l1, and g0
counter (7),
(8)
(8)
Parameter
Parameter
(4)
(3)
areset
(6)
(6)
(7)
(7)
(6)
9.375
Min
Min
300
10
10
(5)
10
10
40
45
10
1
1
1
1
Stratix Device Handbook, Volume 1
DC & Switching Characteristics
±200
Max
Max
460
500
420
700
100
100
(5)
(5)
(5)
60
55
32
32
32
32
Integer
Integer
Integer
Integer
MHz
MHz
MHz
MHz
MHz
Unit
Unit
ps
ps
μs
%
%
4–101
ps
μs
ns

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