EP1SGX40GF1020I6 Altera, EP1SGX40GF1020I6 Datasheet - Page 129

• Manufacturer Part Number: EP1SGX40GF1020I6
• Description: IC STRATIX GX FPGA 40K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX40GF1020I6

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 624
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1020-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 41250
• # I/os (max): 624
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 41250
• Ram Bits: 3423744
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
February 2005
You can use the two-multipliers adder mode for complex multiplications,
which are written as:
The two-multipliers adder mode allows a single DSP block to calculate
the real part [(a
[(a
complex multiplications are possible for data widths up to 9 bits using
four adder/subtractor/accumulator blocks.
two-multipliers adder.
Figure 4–37. Two-Multipliers Adder Mode Implementing Complex Multiply
Four-Multipliers Adder Mode
In the four-multipliers adder mode, the DSP block adds the results of two
first -stage adder/subtractor blocks. One sum of four 18
multipliers or two different sums of two sets of four 9
can be implemented in a single DSP block. The product width for each
multiplier must be the same size. The four-multipliers adder mode is
useful for FIR filter applications.
adder mode.
×
(a + jb)
d) + (b
18
18
×
×
18
(c + jd) = [(a
c)] using one adder, for data widths up to 18 bits. Two
18
×
c) – (b
A
C
B
D
A
D
B
C
×
18
18
18
18
18
18
18
18
d)] using one subtractor and the imaginary part
×
c) – (b
36
36
36
36
Figure 4–38
×
Stratix GX Device Handbook, Volume 1
d)] + j
Subtractor
Adder
DSP Block
×
Figure 4–37
[(a
shows the four multipliers
37
37
×
d) + (b
Stratix GX Architecture
(Imaginary Part)
(A × C) − (B × D)
(A × D) + (B × C)
(Real Part)
×
9-bit multipliers
shows an 18-bit
×
×
18-bit
c)]
4–63