EP1SGX40GF1020I6 Altera, EP1SGX40GF1020I6 Datasheet - Page 240

• Manufacturer Part Number: EP1SGX40GF1020I6
• Description: IC STRATIX GX FPGA 40K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX40GF1020I6

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 624
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1020-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 41250
• # I/os (max): 624
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 41250
• Ram Bits: 3423744
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Timing Model
6–38
Stratix GX Device Handbook, Volume 1
Notes to
(1)
(2)
t
t
t
t
t
t
t
t
t
t
t
INHPLL
OUTCOPLL
INSU
INH
OUTCO
INSU
INH
OUTCO
INSUPLL
INHPLL
OUTCOPLL
Table 6–53. Stratix GX Global Clock External I/O Timing Parameters (Part 2 of 2)
Table 6–54. EP1SGX10 Column Pin Fast Regional Clock External I/O Timing Parameters
Table 6–55. EP1SGX10 Column Pin Regional Clock External I/O Timing Parameters
Symbol
These timing parameters are sample-tested only.
These timing parameters are for column IOE pins. Row IOE pins are 100- to 250-ps slower depending on device,
speed grade, and the specific parameter in question. You should use the Quartus II software to verify the external
timing for any pin.
Symbol
Symbol
Table
6–53:
Hold time for input or bidirectional pin using column IOE
input register with global clock fed by enhanced PLL with
default phase setting
Clock-to-output delay output or bidirectional pin using
column IOE output register with global clock enhanced PLL
with default phase setting
2.114
0.000
2.000
1.035
0.000
0.500
2.245
0.000
2.000
Min
Min
-5 Speed Grade
-5 Speed Grade
Tables 6–54
and row pins for EP1SGX10 devices.
4.728
2.629
4.597
Max
Max
Parameter
through
2.218
0.000
2.000
0.941
0.000
0.500
2.332
0.000
2.000
Min
Min
-6 Speed Grade
-6 Speed Grade
6–59
show the external timing parameters on column
5.078
2.769
4.920
Max
Max
2.348
0.000
2.000
1.070
0.000
0.500
2.666
0.000
2.000
C
Min
Min
-7 Speed Grade
-7 Speed Grade
L O A D
= 10 pF
Conditions
Notes
6.004
3.158
5.635
Max
Max
Altera Corporation
(1),
(2)
June 2006
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns