EP1SGX40GF1020I6 Altera, EP1SGX40GF1020I6 Datasheet - Page 63

• Manufacturer Part Number: EP1SGX40GF1020I6
• Description: IC STRATIX GX FPGA 40K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX40GF1020I6

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 624
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1020-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 41250
• # I/os (max): 624
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 41250
• Ram Bits: 3423744
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
August 2005
Figure 3–10. Misaligned Captured Bits
The dynamic phase selector and synchronizer align the clock and data
based on the power-up of both communicating devices, and the channel
to channel skew. However, the dynamic phase selector and synchronizer
cannot determine the byte boundary, and the data may need to be
byte-aligned. The dynamic phase aligner’s data realignment circuitry
shifts data bits to correct bit misalignments.
The Stratix GX circuitry contains a data-realignment feature controlled by
the logic array. Stratix GX devices perform data realignment on the
parallel data after the deserialization block. The data realignment can be
performed per channel for more flexibility. The data alignment operation
requires a state machine to recognize a specific pattern. The procedure
requires the bits to be slipped on the data stream to correctly align the
incoming data to the start of the byte boundary.
The DPA uses its realignment circuitry and the global clock for data
realignment. Either a device pin or the logic array asserts the internal
rx_channel_data_align node to activate the DPA data-realignment
circuitry. Switching this node from low to high activates the realignment
circuitry and the data being transferred to the logic array is shifted by
one bit. The data realignment block cannot be bypassed. However, if the
rx_channel_data_align is not turned on (through the altvlds
MegaWizard Plug-In Manager), or when it is not toggled, it only acts as a
register latency.
A state machine and additional logic can monitor the incoming parallel
data and compare it against a known pattern. If the incoming data pattern
does not match the known pattern, you can activate the
rx_channel_data_align node again. Repeat this process until the
realigner detects the desired match between the known data pattern and
incoming parallel data pattern.
Correct Alignment
Incorrect Alignment
0
3
1
4
2
5
Source-Synchronous Signaling With DPA
3
6
Stratix GX Device Handbook, Volume 1
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7
5
0
6
1
7
2
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