EP1SGX40GF1020I6 Altera, EP1SGX40GF1020I6 Datasheet - Page 38

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EP1SGX40GF1020I6

Manufacturer Part Number
EP1SGX40GF1020I6
Description
IC STRATIX GX FPGA 40K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet

Specifications of EP1SGX40GF1020I6

Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
624
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1020-FBGA
Family Name
Stratix GX
Number Of Logic Blocks/elements
41250
# I/os (max)
624
Frequency (max)
5GHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.5V
Logic Cells
41250
Ram Bits
3423744
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant

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Figure 2–23. Data Path in Reverse Serial Loopback Mode
2–28
Stratix GX Device Handbook, Volume 1
Active Path
Non-Active Path
Deserializer
Recovery
Clock
Unit
Serializer
Aligner
Word
BIST (Built-In Self Test)
The Stratix GX transceiver has built-in self test modes to aid in debug and
testing. The BIST modes are set in the Stratix GX MegaWizard Plug-In
Manager in the Quartus II software. Only one BIST mode can be set for
any single instance of the transceiver block. The BIST mode applies to all
channels used in a transceiver.
The following is a list of the available BIST modes:
Figures 2–24
BIST incremental data path, respectively.
Channel
BIST PRBS
Aligner
Verifier
PRBS generator and verifier
Incremental mode generator and verifier
High-frequency generator
Low-frequency generator
Mixed-frequency generator
BIST PRBS
Generator
Encoder
8B/10B
and
Matcher
Rate
2–25
are diagrams of the BIST PRBS data path and the
Decoder
8B/10B
Serializer
Byte
Compensation
Deserializer
Phase
FIFO
Byte
Altera Corporation
Incremental
Verifier
Compensation
BIST
Phase
FIFO
June 2006
Generator
BIST

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