EP2S130F1508C4N Altera, EP2S130F1508C4N Datasheet - Page 216

• Manufacturer Part Number: EP2S130F1508C4N
• Description: IC STRATIX II FPGA 130K 1508FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S130F1508C4N

• Number Of Logic Elements/cells: 132540
• Number Of Labs/clbs: 6627
• Total Ram Bits: 6747840
• Number Of I /o: 1126
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1508-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-1870; EP2S130F1508C4N

Duty Cycle Distortion
5–80
Stratix II Device Handbook, Volume 1
Here is an example for calculating the DCD as a percentage for a
non-DDIO output on a row I/O on a -3 device:
If the non-DDIO output I/O standard is SSTL-2 Class II, the maximum
DCD is 95 ps (see
period T is:
To calculate the DCD as a percentage:
Note to
(1)
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
LVDS/
HyperTransport
technology
Table 5–80. Maximum DCD for Non-DDIO Output on Row I/O Pins (Part 2
of 2)
Row I/O Output
T = 1/ f = 1 / 267 MHz = 3.745 ns = 3745 ps
boundary)
boundary)
The DCD specification is based on a no logic array noise condition.
(T/2 – DCD) / T = (3745ps/2 – 95ps) / 3745ps = 47.5% (for low
(T/2 + DCD) / T = (3745ps/2 + 95ps) / 3745ps = 52.5% (for high
Standard
Table
Note (1)
5–80:
Table
5–80). If the clock frequency is 267 MHz, the clock
-3 Devices
180
165
115
95
55
80
85
55
Maximum DCD for Non-DDIO Output
-4 & -5 Devices
180
195
145
125
100
115
85
80
Altera Corporation
Unit
April 2011
ps
ps
ps
ps
ps
ps
ps
ps