EP2S130F1508C4N Altera, EP2S130F1508C4N Datasheet - Page 33

IC STRATIX II FPGA 130K 1508FBGA

EP2S130F1508C4N

Manufacturer Part Number
EP2S130F1508C4N
Description
IC STRATIX II FPGA 130K 1508FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S130F1508C4N

Number Of Logic Elements/cells
132540
Number Of Labs/clbs
6627
Total Ram Bits
6747840
Number Of I /o
1126
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1508-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1870
EP2S130F1508C4N

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Altera
Quantity:
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Quantity:
20 000
Altera Corporation
May 2007
Figure 2–17. Shared Arithmetic Chain, Carry Chain & Register Chain
Interconnects
The C4 interconnects span four LABs, M512, or M4K blocks up or down
from a source LAB. Every LAB has its own set of C4 interconnects to drive
either up or down.
from an LAB in a column. The C4 interconnects can drive and be driven
by all types of architecture blocks, including DSP blocks, TriMatrix
memory blocks, and column and row IOEs. For LAB interconnection, a
primary LAB or its LAB neighbor can drive a given C4 interconnect. C4
interconnects can drive each other to extend their range as well as drive
row interconnects for column-to-column connections.
Routing to Adjacent ALM
Carry Chain & Shared
Arithmetic Chain
Interconnect
Figure 2–18
Local
shows the C4 interconnect connections
Local Interconnect
Routing Among ALMs
in the LAB
Stratix II Device Handbook, Volume 1
ALM 1
ALM 2
ALM 3
ALM 4
ALM 5
ALM 6
ALM 7
ALM 8
Register Chain
Routing to Adjacent
ALM's Register Inpu
Stratix II Architecture
2–25

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