Z9025106PSG Zilog, Z9025106PSG Datasheet - Page 15

• Manufacturer Part Number: Z9025106PSG
• Description: IC 32K 8BIT DTC OTP 42-DIP
• Manufacturer: Zilog

Specifications of Z9025106PSG

• Applications: TV Controller
• Core Processor: Z8
• Program Memory Type: OTP (32 kB)
• Controller Series: Digital Television Controller (DTC)
• Ram Size: 300 x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 27
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 42-DIP (0.600", 15.24mm)
• Processor Series: Z902x
• Core: Z8
• Data Bus Width: 8 bit
• Program Memory Size: 32 KB
• Data Ram Size: 300 B
• Interface Type: I2C
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 27
• Mounting Style: Through Hole
• On-chip Adc: 4 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Acronym
AGND
B
G
GND
H
IRIN
OSDX1, OSDX2 On-Screen Display Dot
P21, P22, P23
P40, P42, P43
P63
R
RESET
SYNC
1.2
Single-Purpose Pin Descriptions
Table 2 lists the single-purpose pin acronyms, pin names, and descriptions.
Table 2
Pin Name(s)
Green
Ground
Horizontal Sync
IR Capture Input
Clock Oscillators
Port 2 bits 1 - 3
Port 4 bit 0, bits 2 and 3
Port 6 bit 3
Red
System Reset
Analog Ground
Blue
Single-Purpose Pin Descriptions
Description
CMOS output of the blue video signal B. Video blue can
be programmed for either polarity.
CMOS output of the green video signal G. Video green
can be programmed for either polarity.
Ground
Input pin for external horizontal synchronization signal
Infrared Remote capture input
These oscillator input and output pins for on-screen
display circuits are connected to an inductor and two
capacitors to generate the character dot clock. The dot
clock frequency determines the character pixel width and
phase synchronized to HSYNC
Bidirectional digital port, configured to read digital data or
to send output to an attached device.
Bidirectional digital port, configured to read digital data or
to send output to an attached device.
P63 input can be read directly at 03H. A negative edge
event is latched to IRQ3. An IRQ3-vectored interrupt
occurs if appropriately enabled. A typical application
places the device in Stop mode when P63 goes Low
(IRQ3 interrupt routine). When P63 subsequently goes
High, a Stop-Mode Recovery is initiated.
CMOS output of the red video signal R. Video red can be
programmed for either polarity.
System reset
Analog Ground
32 KB Television Controller with OSD
PS001301-0800
7