Z9025106PSG Zilog, Z9025106PSG Datasheet - Page 64

• Manufacturer Part Number: Z9025106PSG
• Description: IC 32K 8BIT DTC OTP 42-DIP
• Manufacturer: Zilog

Specifications of Z9025106PSG

• Applications: TV Controller
• Core Processor: Z8
• Program Memory Type: OTP (32 kB)
• Controller Series: Digital Television Controller (DTC)
• Ram Size: 300 x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 27
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 42-DIP (0.600", 15.24mm)
• Processor Series: Z902x
• Core: Z8
• Data Bus Width: 8 bit
• Program Memory Size: 32 KB
• Data Ram Size: 300 B
• Interface Type: I2C
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 27
• Mounting Style: Through Hole
• On-chip Adc: 4 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 38 Master I
Command
10X
000
001
010
011
110
111
Description
Send a Start bit followed by the address byte specified in the I
register, then fetch the acknowledgment bit in I
initialize communication. Nine SCLK cycles are generated.
Send the byte of data specified in the I
acknowledgment bit stored in bit 0. Used in a Write frame. Nine SCLK
cycles are generated.
Send bit 7 of I
(0XXXXXXX), NAK: (1XXXXXXX)), then receive a data byte. Used in a
Read frame when the next data byte is expected. Nine SCLK cycles are
generated. Received data is read in the I
Send bit 7 of I
(0XXXXXXX), NAK: (1XXXXXXX). Used in a Read frame. One SCLK
cycle is generated.
Null operation. Must be used with a Reset bit.
Received one data byte. Used in a Read frame to receive the first data
byte after an address byte is transmitted. Eight SCLK cycles are
generated.
Send Stop bit. One SCLK cycle is generated.
2
C Bus Interface Commands
2
2
C_DATA register as an acknowledgment bit (ACK:
C_DATA register as an acknowledgment bit (ACK:
32 KB Television Controller with OSD
2
C data register, then fetch an
2
C data register.
2
C_DATA (0). Used to
PS001301-0800
2
C data
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