AT43USB325E-AU Atmel, AT43USB325E-AU Datasheet - Page 76

• Manufacturer Part Number: AT43USB325E-AU
• Description: IC USB KEYBOARD CTRLR 64LQFP
• Manufacturer: Atmel
• Series: AVR®r

Specifications of AT43USB325E-AU

• Applications: Keyboard Controller
• Core Processor: AVR
• Program Memory Type: SRAM (16 kB)
• Controller Series: AT43USB
• Ram Size: 512 x 8
• Interface: SPI, 3-Wire Serial
• Number Of I /o: 42
• Voltage - Supply: 4.4 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.3.8
8.3.9
76
AT43USB325
Hub Endpoint 0 Service Routine Register – HCSR0
Function Endpoint 0 Service Routine Register – FCSR0
• Bit 7..4 – Reserved
These bits are reserved in the AT43USB325 and will read as zero.
• Bit 3 – STALL SENT
The USB hardware sets this bit after a STALL has been sent to the host. The firmware uses this
bit when responding to a Get Status[Endpoint] request. It is a read only bit and that is cleared
indirectly by writing a one to the STALL_SENT_ACK bit of the Control and Acknowledge
Register.
• Bit 2 – RX SETUP: Setup Packet Received
This bit is used by control endpoints only to signal to the microcontroller that the USB hardware
has received a valid SETUP packet and that the data portion of the packet is stored in the FIFO.
The hardware will clear all other bits in this register while setting RX SETUP. If interrupt is
enabled, the microcontroller will be interrupted when RX SETUP is set. After the completion of
reading the data from the FIFO, firmware should clear this bit by writing a one to the
RX_SETUP_ACK bit of the Control and Acknowledge Register.
• Bit 1 – RX OUT PACKET
The USB hardware sets this bit after it has stored the data of an OUT transaction in the FIFO.
While this bit is set, the hardware will NAK all OUT tokens. The USB hardware will not overwrite
the data in the FIFO except for an early set-up. RX OUT Packet is used for the following
operations:
Setting this bit causes an interrupt to the microcontroller if the interrupt is enabled. FW clears
this bit after the FIFO contents have been read by writing a one to the RX_OUT_PACKET_ACK
bit of the Control and Acknowledge Register.
• Bit 0 – TX COMPL: Transmit Completed
This bit is used by a control endpoint hardware to signal to the microcontroller that it has suc-
cessfully completed certain transactions. TX Complete is set at the completion of a:
This bit is read only and is cleared indirectly by writing a one to the TX_COMPLETE_ACK bit of
the Control and Acknowledge Register.
1. Control write transactions by a control endpoint.
2. OUT transaction with DATA1 PID to complete the status phase of a control endpoint.
1. Control read data stage.
2. Status stage without data stage.
3. Status stage after a control write transaction.
Function EP0 $1FDD
Function EP0 $1FDF
Read/Write
Initial Value
Bit
R
7
–
–
0
6
–
–
R
0
R
5
–
–
0
R
4
–
–
0
STALL SENT
STALL SENT
R
3
0
RX SETUP
RX SETUP
R
2
0
RX OUT PACKET
RX OUT PACKET
R
1
0
TX COMPLETE
TX COMPLETE
R
0
0
3355C–USB–4/05
HCSR0
FCSR0