CY7C68013-56PVXC Cypress Semiconductor Corp, CY7C68013-56PVXC Datasheet - Page 24

• Manufacturer Part Number: CY7C68013-56PVXC
• Description: IC MCU USB PERIPH HI SPD 56SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68013-56PVXC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 24
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1623

4.1
Table 4-1. FX2 Pin Descriptions
Document #: 38-08012 Rev. *C
TQFP
Note:
5.
128
120
126
127
128
117
118
119
13
19
18
94
95
96
97
21
22
23
24
25
59
60
61
62
63
86
87
88
39
34
99
10
Unused inputs should not be left floating. Tie either HIGH or LOW as appropriate. Outputs should only be pulled up or down to ensure signals at power-up and
in standby.
TQFP
100
CY7C68013 Pin Descriptions
12
18
17
28
77
9
SSOP
56
10
13
16
15
49
QFN
56
42 RESET#
3
6
9
8
AVCC
AGND
DMINUS
DPLUS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
D0
D1
D2
D3
D4
D5
D6
D7
PSEN#
BKPT
Name
[5]
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Power
Power
Type
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Input
Default
N/A
N/A
N/A
H
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Analog V
the chip.
Analog Ground. Connect to ground with as short a path as
possible.
USB D– Signal. Connect to the USB D– signal.
USB D+ Signal. Connect to the USB D+ signal.
8051 Address Bus. This bus is driven at all times. When the
8051 is addressing internal RAM it reflects the internal address.
8051 Data Bus. This bidirectional bus is high-impedance when
inactive, input for bus reads, and output for bus writes. The data
bus is used for external 8051 program and data memory. The data
bus is active only for external bus accesses, and is driven LOW in
suspend.
Program Store Enable. This active-LOW signal indicates an 8051
code fetch from external memory. It is active for program memory
fetches from 0x2000–0xFFFF when the EA pin is LOW, or from
0x0000–0xFFFF when the EA pin is HIGH.
Breakpoint. This pin goes active (HIGH) when the 8051 address
bus matches the BPADDRH/L registers and breakpoints are
enabled in the BREAKPT register (BPEN = 1). If the BPPULSE bit
in the BREAKPT register is HIGH, this signal pulses HIGH for eight
12-/24-/48-MHz clocks. If the BPPULSE bit is LOW, the signal
remains HIGH until the 8051 clears the BREAK bit (by writing 1 to
it) in the BREAKPT register.
Active LOW Reset. Resets the entire chip. This pin is normally
tied to V
capacitor.
CC
CC
through a 100K resistor, and to GND through a 0.1- F
. This signal provides power to the analog section of
Description
CY7C68013
Page 24 of 52