CY7C68013-56PVXC Cypress Semiconductor Corp, CY7C68013-56PVXC Datasheet - Page 36

• Manufacturer Part Number: CY7C68013-56PVXC
• Description: IC MCU USB PERIPH HI SPD 56SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68013-56PVXC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 24
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1623

Table 5-1. FX2 Register Summary (continued)
Document #: 38-08012 Rev. *C
Hex Size Name
CC
CD
9A
9B
9C
9D
9E
A0
A1
A2
A3
A8
A9
AA
AB
AC
AD
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
C0
C1
C2
C8
C9
CA
CB
CE
D0
D1
D8
D9
E0
E1
E8
E9
9F
F0
F1
F8
F9
1
1
1
1
1
1
1
1
1
5
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6
1
1
1
1
1
1
2
1
7
1
7
1
7
1
7
1
7
1
7
AUTOPTRH1
AUTOPTRL1
reserved
AUTOPTRH2
AUTOPTRL2
reserved
IOC
INT2CLR
INT4CLR
reserved
IE
reserved
EP2468STAT
EP24FIFOFLGS
EP68FIFOFLGS
reserved
AUTOPTRSET-
UP
IOD
IOE
OEA
OEB
OEC
OED
OEE
reserved
IP
reserved
EP01STAT
GPIFTRIG
reserved
GPIFSGLDATH
GPIFSGLDATLX
GPIFSGLDATL-
NOX
SCON1
SBUF1
reserved
T2CON
reserved
RCAP2L
RCAP2H
TL2
TH2
reserved
PSW
reserved
EICON
reserved
ACC
reserved
EIE
reserved
B
reserved
EIP
reserved
[7]
[7]
[7]
[7]
[7]
[7]
[7]
[7]
[7]
[7]
[7]
[7]
[7]
[7]
[7]
[7]
[7]
[7] [6]
[7]
[7]
[7]
[7]
[7]
[7]
[7]
[7]
[7]
[7]
Description
Autopointer 1 Address H
Autopointer 1 Address L
Autopointer 2 Address H
Autopointer 2 Address L
Port C (bit addressable)
Interrupt 2 clear
Interrupt 4 clear
Interrupt Enable (bit addres-
sable)
Endpoint 2,4,6,8 status flags
Endpoint 2,4 slave FIFO sta-
tus flags
Endpoint 6,8 slave FIFO sta-
tus flags
Autopointer 1&2 Setup
Port D (bit addressable)
Port E (NOT bit addressable)
Port A Output Enable
Port B Output Enable
Port C Output Enable
Port D Output Enable
Port E Output Enable
Interrupt Priority (bit addres-
sable)
Endpoint 0&1 Status
Endpoint 2,4,6,8 GPIF slave
FIFO Trigger
GPIF Data H (16-bit mode
only)
GPIF Data L w/ Trigger
GPIF Data L w/ No Trigger
Serial Port 1 Control (bit ad-
dressable)
Serial Port 1 Data Buffer
Timer/Counter 2 Control (bit
addressable)
Capture for Timer 2, auto-re-
load, up-counter
Capture for Timer 2, auto-re-
load, up-counter
Timer 2 reload L
Timer 2 reload H
Program Status Word (bit ad-
dressable)
External Interrupt Control
Accumulator (bit address-
able)
External Interrupt Enable(s)
B (bit addressable)
External Interrupt Priority
Control
SMOD1
SM0_1
DONE
EP8F
A15
A15
D15
TF2
D15
CY
A7
A7
D7
EA
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
b7
x
x
0
0
0
1
0
1
1
EP4PF
EP8PF
SM1_1
EP8E
EXF2
A14
A14
ES1
PS1
D14
D14
AC
b6
A6
A6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
0
0
0
1
1
1
x
x
EP4EF
EP8EF
SM2_1
ERESI
RCLK
EP6F
A13
A13
ET2
PT2
D13
D13
b5
A5
A5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
F0
D5
D5
0
0
0
1
1
x
x
REN_1
EP4FF
EP8FF
EP6E
TCLK
RESI
ES0
PS0
RS1
EX6
PX6
A12
A12
D12
D12
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
b4
A4
A4
x
x
0
0
0
EXEN2
TB8_1
EP4F
INT6
RS0
EX5
PX5
A11
A11
ET1
PT1
D11
D11
b3
A3
A3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
x
x
0
0
0
0
0
APTR2INC
EP1INBSY EP1OUTBSY
EP2PF
EP6PF
RB8_1
EP4E
EX1
PX1
D10
TR2
D10
EX4
PX4
A10
A10
RW
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
OV
D2
D2
b2
A2
A2
x
x
0
APTR1INC
EP2EF
EP6EF
EP2F
EP1
TI_1
CT2
EI²C
PI²C
ET0
PT0
b1
A9
A1
A9
A1
D1
D1
D1
D1
D1
D1
D1
D1
D9
D1
D1
D1
D1
D1
D1
D9
F1
D1
D1
x
x
0
APTREN
EP0BSY
EP2FF
EP6FF
CPRL2
CY7C68013
EUSB
PUSB
EP2E
RI_1
EX0
PX0
EP0
A8
A0
A8
A0
D0
D0
D0
D0
D0
D0
D0
D0
D8
D0
D0
D0
D0
D0
D0
D8
D0
D0
b0
P
x
x
0
Page 36 of 52
00000000
00000000
00000000
00000000
00000000
01011010
00100010
01100110
00000110
00000000
00000000
00000000
00000000
00000000
10000000
00000000
10000xxx brrrrbbb
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
01000000
00000000
11100000
00000000
11100000
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
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Default
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
W
W
R
R
R
R
R