STPCI2GDYI STMicroelectronics, STPCI2GDYI Datasheet - Page 3

• Manufacturer Part Number: STPCI2GDYI
• Description: IC SYSTEM-ON-CHIP X86 516-PBGA
• Manufacturer: STMicroelectronics

Specifications of STPCI2GDYI

• Applications: Graphics Controller
• Core Processor: x86
• Controller Series: STPC® Atlas
• Interface: UART
• Number Of I /o: 16
• Voltage - Supply: 2.45 V ~ 2.7 V
• Operating Temperature: -40°C ~ 115°C
• Mounting Type: Surface Mount
• Package / Case: 516-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant

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TFT Interface
Programmable panel size up to 1024 by 1024
Support for VGA and SVGA active matrix TFT
Support for XGA and SXGA active matrix
Programmable image positionning.
Programmable blank space insertion in text
Programmable horizontal and vertical image
One fully programmable PWM (Pulse Width
Supports PanelLink
PCI Controller
Compatible with PCI 2.1 specification.
Integrated PCI arbitration interface. Up to 3
Translation of PCI cycles to ISA bus.
Translation of ISA master initiated cycle to
Support for burst read/write from PCI master.
PCI clock is 1/2, 1/3 or 1/4 Host bus clock.
ISA master/slave
Generates the ISA clock from either
Supports programmable extra wait state for
Supports I/O recovery time for back to back
Fast Gate A20 and Fast reset.
Supports the single ROM that C, D, or E.
Supports flash ROM.
pixels.
flat panels with 9, 12, 18-bit interface (1 pixel
per clock).
TFT flat panels with 2 x 9-bit interface (2
pixels per clock).
mode.
expansion in graphic mode.
Modulator) signals to adjust the flat panel
brightness and contrast.
transmitter externally for high resolution
panel interface.
masters can connect directly. External logic
allows for greater than 3 masters.
PCI.
14.318MHz oscillator clock or PCI clock
ISA cycles
I/O cycles.
blocks shares with F block BIOS ROM.
TM
high speed serial
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Supports ISA hidden refresh.
Buffered DMA & ISA master cycles to reduce
Local Bus interface
Multiplexed with ISA/DMA interface.
Low latency asynchronous bus
16-bit data bus with word steering capability.
Programmable timing (Host clock granularity)
4 Programmable Flash Chip Select.
8 Programmable I/O Chip Select.
I/O device timing (setup & recovery time)
Supports 32-bit Flash burst.
2-level hardware key protection for Flash boot
Supports 2 banks of 32MB flash devices with
Reallocatable Memory space Windows
EIDE Interface
Supports PIO
Transfer Rates to 22 MBytes/sec
Supports up to 4 IDE devices
Concurrent channel operation (PIO modes) -
Support for PIO mode 3 & 4.
Individual drive timing for all four IDE devices
Supports both legacy & native IDE modes
Supports hard drives larger than 528MB
Support for CD-ROM and tape peripherals
Backward compatibility with IDE (ATA-1).
Integrated Peripheral Controller
2X8237/AT compatible 7-channel DMA
2X8259/AT compatible interrupt Controller. 16
Three 8254 compatible Timer/Counters.
Co-processor error support logic.
Supports external RTC (Not in Local Bus
bandwidth utilization of the PCI and Host
bus.
programmable
block protection.
boot block shadowed to 0x000F0000.
4 x 32-Bit Buffer FIFOs per channel
controller.
interrupt inputs - ISA and PCI.
Mode).
STPC® ATLAS
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