STPCI2GDYI STMicroelectronics, STPCI2GDYI Datasheet - Page 91

• Manufacturer Part Number: STPCI2GDYI
• Description: IC SYSTEM-ON-CHIP X86 516-PBGA
• Manufacturer: STMicroelectronics

Specifications of STPCI2GDYI

• Applications: Graphics Controller
• Core Processor: x86
• Controller Series: STPC® Atlas
• Interface: UART
• Number Of I /o: 16
• Voltage - Supply: 2.45 V ~ 2.7 V
• Operating Temperature: -40°C ~ 115°C
• Mounting Type: Surface Mount
• Package / Case: 516-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant

6.4.3. MEMORY INTERFACE
6.4.3.1. Introduction
In order to achieve SDRAM memory interfaces
which work at clock frequencies of 90 MHz and
above, careful consideration has to be given to the
timing of the interface with all the various electrical
and physical constraints taken into consideration.
The guidelines described below are related to
SDRAM components on DIMM modules. For
applications where the memories are directly
soldered to the motherboard, the PCB should be
laid out such that the trace lengths fit within the
constraints shown here. The traces could be
slightly shorter since the extra routing on the
6.4.3.3. Board Layout Issues
The physical layout of the motherboard PCB
assumed in this presentation is as shown in
6-22. Because all of the memory interface signal
balls are located in the same region of the STPC
device, it is possible to orientate the device to
reduce the trace lengths. The worst case routing
length to the DIMM1 is estimated to be 100 mm.
Solid power and ground planes are a must in order
to provide good return paths for the signals and to
Figure 6-21. Clock Scheme
CONTROLLER
SDRAM
PLL
PLL
MCLKO
MCLKI
MA[ ] + Control
MD[63:0]
Figure
DIMM PCB is no longer present but it is then up to
the user to verify the timings.
6.4.3.2. SDRAM Clocking Scheme
The SDRAM Clocking Scheme deserves a special
mention here. Basically the memory clock is
generated on-chip through a PLL and goes directly
to the MCLKO output pin of the STPC. The
nominal frequency is 90 MHz. Because of the high
load presented to the MCLK on the board by the
DIMMs it is recommended to rebuffer the MCLKO
signal on the board and balance the skew to the
clock ports of the different DIMMs and the MCLKI
input pin of STPC.
reduce EMI and noise. Also there should be ample
high frequency decoupling between the power and
ground planes to provide a low impedance path
between the planes for the return paths for signal
routings which change layers. If possible, the
traces should be routed adjacent to the same
power or ground plane for the length of the trace.
For the SDRAM interface, the most critical signal
is the clock. Any skew between the clocks at the
STPC® ATLAS
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