STPCI2GDYI STMicroelectronics, STPCI2GDYI Datasheet - Page 77

• Manufacturer Part Number: STPCI2GDYI
• Description: IC SYSTEM-ON-CHIP X86 516-PBGA
• Manufacturer: STMicroelectronics

Specifications of STPCI2GDYI

• Applications: Graphics Controller
• Core Processor: x86
• Controller Series: STPC® Atlas
• Interface: UART
• Number Of I /o: 16
• Voltage - Supply: 2.45 V ~ 2.7 V
• Operating Temperature: -40°C ~ 115°C
• Mounting Type: Surface Mount
• Package / Case: 516-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant

6.3.3. SDRAM
The STPC provides all the signals for SDRAM
control. Up to 128 MBytes of main memory are
supported. All Banks must be 64 bits wide. Up to 4
memory banks are available when using 16Mbit
devices. Only up to 2 banks can be connected
when using 64Mbit and 128Mbit components due
to the reallocation of CS2# and CS3# signals. This
is described in
Graphics memory resides at the beginning of Bank
0. Host memory begins at the top of graphics
Figure 6-5. One Memory Bank with 4 Chips (16-bit)
For other implementations like 32-bit SDRAM
devices, refers to the SDRAM controller signal
Refer to
Section 4.5.3.
MCLKI
MCLKO
DQM[7:0]
MD[63:0]
CS0#
MA[12:0]
BA[1:0]
RAS0#
CAS0#
WE#
Table 6-4
for detailed timing constraints.
and
10pF
Reference Knot
Table
6-5.
DQM[7:6]
MD[63:48]
MCLKD
Length(MCLKI+1ns(+/- 0.5ns)) = Length(MCLKx)
memory and extends to the top of populated
SDRAM. Bank 0 must always be populated.
Figure
typical implementations.
The purpose of the serial resistors is to reduce
signal oscillation and EMI by filtering line
reflections. The capacitance in
filtering effect too, while it is used for propagation
delay compensation in the 2 other figures.
multiplexing and address mapping described in
the following
6-5,
DQM[5:4]
MD[47:32]
MCLKC
Figure 6-6
Table 6-4
DQM[3:2]
MD[31:16]
MCLKB
and
and
Figure 6-7
Table
with x = {A,B,C,D}
STPC® ATLAS
Figure 6-5
6-5.
MCLKA
DQM[1:0]
MD[15:0]
show some
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