EZ80190AZ050EG Zilog, EZ80190AZ050EG Datasheet - Page 104

• Manufacturer Part Number: EZ80190AZ050EG
• Description: IC WEBSERVER 50MHZ XTEMP 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050EG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3865; EZ80190AZ050EG

PS006614-1208
SDA Signal
SCL Signal
Acknowledge
Start Condition
I
can hold the SCL line Low to force the transmitter into a WAIT state. Data transfer then
continues when the receiver is ready for another byte of data and releases SCL.
Data transfer with an ACK function is obligatory. The ACK-related clock pulse is gener-
ated by the master. The transmitter releases the SDA line (High) during the ACK clock
pulse. The receiver must pull down the SDA line during the ACK clock pulse so that it
remains Low during the High period of this clock pulse. See
A receiver that is addressed is obliged to generate an ACK after each byte is received.
When a slave receiver does not acknowledge the slave address (that is, the slave receiver
is unable to receive because it is performing some real-time function), the data line must
be left High by the slave. The master then generates a STOP condition to abort the trans-
fer.
If a slave receiver acknowledges the slave address, but cannot receive any more data
bytes, the master must abort the transfer. The abort is indicated by the slave generating the
Not Acknowledge (NACK) on the first byte to follow. The slave leaves the data line High
and the master generates the STOP condition.
If a master receiver is involved in a transfer, it must signal the end of the data transfer to
the slave transmitter by not generating an ACK on the final byte clocked out of the slave.
The slave transmitter must release the data line to allow the master to generate a STOP or
a repeated START condition.
2
C Acknowledge (ACK). Data is transferred with the msb first, see
S
MSB
1
2
Figure 18. I
Acknowledge
From Receiver
8
9
2
C Frame Structure
Clock Line Held Low By Receiver
1
Acknowledge
From Receiver
Figure 19
ACK
9
Product Specification
Figure
I2C Serial I/O Interface
on page 95.
Stop Condition
18. A receiver
P
94