EZ80190AZ050EG Zilog, EZ80190AZ050EG Datasheet - Page 33
![IC WEBSERVER 50MHZ XTEMP 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80190AZ050EG
Manufacturer Part Number
EZ80190AZ050EG
Description
IC WEBSERVER 50MHZ XTEMP 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80190AZ050SG.pdf
(221 pages)
Specifications of EZ80190AZ050EG
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80190x
Core
eZ80
Data Bus Width
8 bit
Program Memory Type
ROMLess
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3865
EZ80190AZ050EG
EZ80190AZ050EG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EZ80190AZ050EG
Manufacturer:
TYCO
Quantity:
120
Company:
Part Number:
EZ80190AZ050EG
Manufacturer:
Zilog
Quantity:
70
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Register Map
Table 2. Register Map
PS006614-1208
Address
(hex)
Programmable Reload Counter/Timers
80
81
82
83
84
85
86
87
88
89
Note:
Mnemonic
TMR0_CTL
TMR0_DR_L
TMR0_RR_L
TMR0_DR_H
TMR0_RR_H
TMR1_CTL
TMR1_DR_L
TMR1_RR_L
TMR1_DR_H
TMR1_RR_H
TMR2_CTL
TMR2_DR_L
TMR2_RR_L
TMR2_DR_H
TMR2_RR_H
TMR3_CTL
All on-chip peripheral registers are accessed in the I/O address space. All I/O operations
employ 16-bit addresses. The upper byte of the 24-bit address bus is forced to
(ADDR[23:16] =
within the range of
value from
programmed for the I/O Chip Selects overlap the
Registers at unused addresses within the
als are not implemented. READ access to such addresses return unpredictable values and
WRITE access produces no effect.
00h
to
Name
Timer 0 Control Register
Timer 0 Data Register—Low Byte
Timer 0 Reload Register—Low Byte
Timer 0 Data Register—High Byte
Timer 0 Reload Register—High Byte
Timer 1 Control Register
Timer 1 Data Register—Low Byte
Timer 1 Reload Register—Low Byte
Timer 1 Data Register—High Byte
Timer 1 Reload Register—High Byte
Timer 2 Control Register
Timer 2 Data Register—Low Byte
Timer 2 Reload Register—Low Byte
Timer 2 Data Register—High Byte
Timer 2 Reload Register—High Byte
Timer 3 Control Register
00h
FFh
80h
) during all I/O operations. All I/O operations using 16-bit addresses
. External I/O Chip Selects are not generated if the address space
to
FFh
are routed to the on-chip peripherals; where
Table 2
80h
lists the register map for the eZ80190 device.
to
FFh
80h
range assigned to on-chip peripher-
to
FFh
Reset
address range.
(hex)
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
Product Specification
Access
CPU
R/W
R/W
R/W
R/W
W
W
W
W
W
W
R
R
R
R
R
R
xx
Register Map
00h
is any
eZ80190
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