EZ80190AZ050EG Zilog, EZ80190AZ050EG Datasheet - Page 61

• Manufacturer Part Number: EZ80190AZ050EG
• Description: IC WEBSERVER 50MHZ XTEMP 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050EG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3865; EZ80190AZ050EG

Memory Chip Select Priority
PS006614-1208
Reset States
Memory Chip Select Example
•
If the upper and lower bounds are set to the same value, such that CSx_UBR = CSx_LBR,
then a particular Chip Select is valid for, at most, a single 64 KB page. Again, if a higher-
priority Chip Select also encompasses the same set of addresses, then the lower-priority
Chip Select is not generated.
A lower-numbered Chip Select is granted priority over a higher-numbered Chip Select. If
the Chip Select 0 address space overlaps the Chip Select 1 address space, Chip Select 0 is
active. If the address range programmed for any Chip Select signal overlaps with the
address of internal RAM, then RAM is accorded higher priority. If the particular Chip
Select(s) feature an address range that overlaps with the RAM address, then when RAM is
selected, the Chip Select signal is not asserted.
On reset, Chip Select 0 is active for all addresses, because its Lower Bound register resets
to
Lower and Upper Bound registers reset to
The use of Memory Chip Selects is displayed in
trol register values listed in
enabled and configured for memory addresses. CS0, CS1, and CS2 are all configured such
that their address spaces do not overlap. CS3 is allocated an address space that spans the
entire 16 MB of available memory. Consequently, CS3 overlaps the address spaces for
CS0, CS1, and CS2. However, because CS3 is the lowest-priority Chip Select, it only
becomes active where it does not overlap either CS0, CS1, or CS2.
0000h
Depending upon the instruction, either RD or WR are activated (driven Low)
and its Upper Bound register resets to
Table 17
on page 52. In this example, all 4 Chip Selects are
0000h
FFFFh
Figure 8
.
. All of the other Chip Select
on page 52. The associated con-
Chip Selects and Wait States
Product Specification
eZ80190
51