EZ80190AZ050EG Zilog, EZ80190AZ050EG Datasheet - Page 28

• Manufacturer Part Number: EZ80190AZ050EG
• Description: IC WEBSERVER 50MHZ XTEMP 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050EG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3865; EZ80190AZ050EG

Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device (Continued)
PS006614-1208
Pin
No.
77
78
Symbol
PD1
MOSI0
RxD0
SDA0
PD2
SCK0
RTS0
Function
GPIO Port D
Master Out
Slave In
Receive Data
I
GPIO Port D
SPI Serial
Clock
Request to
Send
2
C Serial Data Input/Output
Signal Direction
Input/Output
Input/Output
Input
Input/Output
Input/Output
Output, Active Low The RTS0 pin carries the modem-control signal
Description
The PD1 pin can be used for GPIO. It can be
individually programmed as an input or output
and can also be used individually as an interrupt
input. Each Port D pin, when programmed as an
output, can be selected to be an open-drain or
open-source output. Port D is multiplexed with
one channel of the UZI interface.
The MOSI line is configured as an output when
the eZ80190 device is an SPI master device and
as an input when the eZ80190 device is an SPI
slave device. This signal is multiplexed with PD1.
The RxD0 pin is used by the UART to receive
asynchronous serial data. This signal is
multiplexed with PD1.
The SDA0 pin carries the I
signal is multiplexed with PD1.
The PD2 pin can be used for GPIO. It can be
individually programmed as an input or output
and can also be used individually as an interrupt
input. Each Port D pin, when programmed as an
output, can be selected to be an open-drain or
open-source output. Port D is multiplexed with
one channel of the UZI interface.
The SPI serial clock signal is multiplexed with
PD2.
from the UART. This signal is multiplexed with
PD2.
Product Specification
2
C data signal. This
Architectural Overview
18