EZ80190AZ050EG Zilog, EZ80190AZ050EG Datasheet - Page 122

• Manufacturer Part Number: EZ80190AZ050EG
• Description: IC WEBSERVER 50MHZ XTEMP 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050EG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3865; EZ80190AZ050EG

PS006614-1208
I
Table 56. I
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
[7:0]
SRR
2
C Software Reset Register
To ensure correct detection of START and STOP conditions on the bus, the I
ple the I
bus. The sampling frequency should therefore be at least 1 MHz (4 MHz in FAST mode)
to guarantee correct operation with other bus masters.
The I
clock and the value in the I2Cx_CCR bits 2 to 0. The bus clock speed generated by the I
in MASTER mode is determined by the frequency of the input clock and the values in
I2Cx_CCR[2:0] and I2Cx_CCR[6:3].
The I2Cx_SRR register, listed in
any value to this register will perform a software reset of the I
2
C Software Reset Register
2
Value
00h–FFh Writing any value to this register performs a software reset of the
C sampling frequency is determined by the frequency of the eZ80190 device system
2
C bus at least ten times faster than the bus clock speed of the fastest master on the
W
X
7
Description
I
2
C module.
W
X
6
W
X
5
Table 56
W
X
4
(I2C0_SRR = CDh, I2C1_SRR = DDh)
on page 112, is a Write Only register. Writing
W
X
3
W
X
2
2
C module.
Product Specification
W
1
X
I2C Serial I/O Interface
W
2
X
0
C must sam-
2
C
112