MPC8313CVRADDB Freescale Semiconductor, MPC8313CVRADDB Datasheet - Page 48

MPU POWERQUICC II PRO 516-PBGA

MPC8313CVRADDB

Manufacturer Part Number
MPC8313CVRADDB
Description
MPU POWERQUICC II PRO 516-PBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8313CVRADDB

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
267MHz
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
516-PBGA
Processor Series
MPC8xxx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
MPC8313E-RDB
Maximum Clock Frequency
400 MHz
Operating Supply Voltage
- 0.3 V to + 1.26 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
16 KB
I/o Voltage
2.5 V
Interface Type
I2C, SPI, UART
Minimum Operating Temperature
- 40 C
Program Memory Type
EEPROM/Flash
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8313CVRADDB
Manufacturer:
FREESCAL
Quantity:
672
Part Number:
MPC8313CVRADDB
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Enhanced Local Bus
11.2
Table 46
Figure 36
48
Local bus cycle time
Input setup to local bus clock
Input hold from local bus clock
LALE output fall to LAD output transition (LATCH hold time)
LALE output fall to LAD output transition (LATCH hold time)
LALE output fall to LAD output transition (LATCH hold time)
LALE output rise to LCLK negative edge
LALE output fall to LCLK negative edge
LALE output fall to LCLK negative edge
LALE output fall to LCLK negative edge
Local bus clock to output valid
Local bus clock to output high impedance for LAD
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of
3. All signals are measured from NV
4. Input timings are measured at the pin.
5.t
6.t
7.t
8. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
inputs and t
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock one (1).
LCLK0 (for all other inputs).
signaling levels.
LBOTOT1
than the load on LAD output pins.
LBOTOT2
the load on LAD output pins.
LBOTOT3
output pins.
through the component pin is less than or equal to the leakage current specification.
describes the general timing parameters of the local bus interface.
Local Bus AC Electrical Specifications
and t
and t
and t
provides the AC test load for the local bus.
(first two letters of functional block)(reference)(state)(signal)(state)
LALETOT2
LALETOT3
LALETOT1
MPC8313E PowerQUICC
Parameter
should be used when RCWH[LALE] is set and the load on LALE output pin is at least 10 pF less than
should be used when RCWH[LALE] is set and the load on LALE output pin equals to the load on LAD
should be used when RCWH[LALE] is not set and the load on LALE output pin is at least 10 pF less
Output
Table 46. Local Bus General Timing Parameters
DD
/2 of the rising/falling edge of LCLK0 to 0.4 × NV
Figure 36. Local Bus AC Test Load
Z
0
II Pro Processor Hardware Specifications, Rev. 3
= 50 Ω
t
t
t
Symbol
t
t
t
t
(first two letters of functional block)(signal)(state)(reference)(state)
LALETOT1
LALETOT2
LALETOT3
t
t
LALEHOV
LBOTOT1
LBOTOT2
LBOTOT3
t
t
LBKHOV
LBKHOZ
for outputs. For example, t
LBIVKH
LBIXKH
t
LBK
LBK
1
R
clock reference (K) goes high (H), in this case for
L
= 50 Ω
–1.5
–5.0
–4.5
Min
1.0
1.5
2.5
15
7
3
DD
NV
of the signal in question for 3.3-V
DD
LBIXKH1
/2
Max
3.0
3
4
Freescale Semiconductor
symbolizes local bus
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
3, 4
3, 4
for
6
2
5
7
5
6
7
3
8

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