MC68340AG16VE Freescale Semiconductor, MC68340AG16VE Datasheet - Page 193

• Manufacturer Part Number: MC68340AG16VE
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16VE

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

5.5.3.1.3 Type III—Faults During MOVEM Operand Transfer. Bus faults that occur as a
result of MOVEM operand transfer are classified as type III faults. MOVEM instruction
prefetch faults are type II faults.
Type III faults cause an immediate exception that aborts the current instruction. None of
the registers altered during execution of the faulted instruction are restored prior to
execution of the fault handler. This includes any register predecremented as a result of the
effective address calculation or any register overwritten during instruction execution. Since
postincremented registers are not updated until the end of an instruction, the register
retains its pre-instruction value unless overwritten by operand movement.
The SSW for faults in this category contains the following bit pattern:
MV is set, indicating that MOVEM should be continued from the point where the fault
occurred upon return from the exception handler. TR, B1, and B0 are set if a
corresponding exception is pending when the bus error exception is taken. IN is set if a
bus fault occurs while prefetching an opcode or an extension word during instruction
restart. RW, LG, SIZ, and FUNC all reflect the type of bus cycle that caused the fault. All
write faults have the RR bit set to indicate that the write should be rerun upon return from
the exception handler.
The remainder of the stack frame contains sufficient information to continue MOVEM with
operand transfer following a faulted transfer. The address of the next operand to be
transferred, incremented or decremented by operand size, is stored in the faulted address
location ($08). The stacked transfer counter is set to 16 minus the number of transfers
attempted (including the faulted cycle). Refer to Figure 5-12 for the stacking format.
5.5.3.1.4 Type IV—Faults During Exception Processing. The fourth type of fault occurs
during exception processing. If this exception is a second address or bus error, the
machine halts in the double bus fault condition. However, if the exception is one that
causes a four- or six-word stack frame to be written, a bus cycle fault frame is written
below the faulted exception stack frame.
The SSW for a fault within an exception contains the following bit pattern:
TR, B1, and B0 are set if a corresponding exception is pending when the bus error
exception is taken.
The contents of the faulted exception stack frame are included in the bus fault stack
frame. The pre-exception SR and the format/vector word of the faulted frame are stacked.
The type of exception can be determined from the format/vector word. If the faulted
exception stack frame contains six words, the PC of the instruction that caused the initial
5-56
15
15
1
0
14
14
0
1
13
13
0
0
TR
12
TR
12
11
B1
Freescale Semiconductor, Inc.
11
B1
For More Information On This Product,
10
B0
10
B0
MC68340 USER’S MANUAL
Go to: www.freescale.com
RR
9
0
9
8
0
8
0
IN
7
0
7
RW
6
1
6
LG
LG
5
5
4
4
SIZ
SIZ
3
3
2
2
MOTOROLA
FUNC
FUNC
0
0