MC68340AG16VE Freescale Semiconductor, MC68340AG16VE Datasheet - Page 283

• Manufacturer Part Number: MC68340AG16VE
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16VE

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

6.7.6 Source Address Register (SAR)
The SAR is a 32-bit register that contains the address of the source operand used by the
DMA to access memory or peripheral registers. This register is accessible in either
supervisor or user space. The SAR can always be read or written to when the DMA
module is enabled (i.e., the STP bit in the MCR is cleared).
SAR1, SAR2
U = Unaffected by reset
During the DMA read cycle, the SAR drives the address on the address bus. This register
can be programmed to increment (CCR SAPI bit set) or remain constant (CCR SAPI bit
cleared) after each operand transfer.
The register is incremented using unsigned arithmetic and will roll over if overflow occurs.
For example, if the register contains $FFFFFFFF and is incremented by 1, it will roll over
to $00000000. This register is incremented by 1, 2, or 4, depending on the size of the
operand and the memory starting address. If the operand size is byte, then the register is
always incremented by 1. If the operand size is word and the starting address is even-
word aligned, then the register is incremented by 2. If the operand size is long word and
the address is even-word aligned, then the register is incremented by 4. The SAR value
must be aligned to an even-word boundary if the transfer size is word or long word;
otherwise, the CSR CONF bit is set, and the transfer does not occur.
When read, this register always contains the next source address. If a bus error
terminates the transfer, this register contains the next source address that would have
been run had the error not occurred.
6.7.7 Destination Address Register (DAR)
The DAR is a 32-bit register that contains the address of the destination operand used by
the DMA to write to memory or peripheral registers. This register is accessible in either
supervisor or user space. The DAR can always be read or written to when the DMA
module is enabled (i.e., the STP bit in the MCR is cleared).
MOTOROLA
RESET:
RESET:
A31
A15
31
15
U
U
A30
A14
30
14
U
U
A29
A13
29
13
U
U
A28
A12
28
12
U
U
Freescale Semiconductor, Inc.
A27
A11
27
11
U
U
For More Information On This Product,
A26
A10
26
10
U
U
MC68340 USER’S MANUAL
Go to: www.freescale.com
A25
25
A9
U
9
U
A24
24
A8
U
8
U
A23
23
A7
U
7
U
A22
22
A6
U
6
U
A21
21
A5
U
5
U
A20
20
A4
U
4
U
A19
19
A3
U
3
U
Supervisor/User
A18
18
A2
U
2
U
$78C, $7AC
A17
17
A1
U
1
U
A16
16
A0
6- 33
U
0
U