MC68340AG16VE Freescale Semiconductor, MC68340AG16VE Datasheet - Page 59

• Manufacturer Part Number: MC68340AG16VE
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16VE

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

3.2.3.5 WORD OPERAND TO 16-BIT PORT, ALIGNED. The MC68340 drives the
address bus with the desired address and the size pins to indicate a word operand.
For a read operation, the slave responds by placing the data on bits 15–0 of the data bus
and asserting DSACK1 to indicate a 16-bit port. When DSACK1 is asserted, the
MC68340 reads the data on the data bus and terminates the cycle.
For a write operation, the MC68340 drives the word operand on bits 15–0 of the data bus.
The slave device then reads the entire operand from bits 15–0 of the data bus and asserts
DSACK1 to terminate the bus cycle.
3.2.3.6 LONG-WORD OPERAND TO 8-BIT PORT, ALIGNED. The MC68340 drives the
address bus with the desired address and the SIZx pins to indicate a long-word operand.
For a read operation, shown in Figure 3-3, the slave responds by placing the most
significant byte of the operand on bits 15–8 of the data bus and asserting DSACK0 to
indicate an 8-bit port. The MC68340 reads the most significant byte of the operand (byte
0) from bits 15–8 and ignores bits 7–0. The MC68340 then decrements the transfer size
counter, increments the address, initiates a new cycle, and reads byte 1 of the operand
from bits 15–8 of the data bus. The MC68340 repeats the process of decrementing the
transfer size counter, incrementing the address, initiating a new cycle, and reading a byte
to transfer the remaining two bytes.
For a write operation, shown in Figure 3-4, the MC68340 drives the two most significant
bytes of the operand on bits 15–0 of the data bus. The slave device then reads only the
most significant byte of the operand (byte 0) from bits 15–8 of the data bus and asserts
DSACK0 to indicate reception and an 8-bit port. The MC68340 then decrements the
transfer size counter, increments the address, and writes byte 1 of the operand to bits
15–8 of the data bus. The MC68340 continues to decrement the transfer size counter,
increment the address, and write a byte to transfer the remaining two bytes to the slave
device.
3-10
LONG-WORD OPERAND
DATA BUS
WORD OPERAND
DATA BUS
CYCLE 1
CYCLE 1
CYCLE 2
CYCLE 3
CYCLE 4
15
D15
Freescale Semiconductor, Inc.
D15
31
OP0
OP0
For More Information On This Product,
OP0
OP0
OP1
OP2
OP3
D8
D8
D7
MC68340 USER’S MANUAL
23
OP1
OP1
D7
Go to: www.freescale.com
(OP1)
(OP1)
(OP3)
(OP3)
OP1
D0
0
D0
15
OP2
SIZ1
1
SIZ1
7
0
1
1
0
OP3
SIZ0
0
SIZ0
0
0
1
0
1
A0
0
A0
0
1
0
1
DSACK1
DSACK1
0
1
1
1
1
DSACK0
DSACK0
X
0
0
0
0
MOTOROLA