MPC8358EZQAGDGA Freescale Semiconductor, MPC8358EZQAGDGA Datasheet
MPC8358EZQAGDGA
Specifications of MPC8358EZQAGDGA
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MPC8358EZQAGDGA Summary of contents
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... Rev locate any updates for this document, refer to the MPC8360E product summary page on our website listed on the back cover of this document or contact your Freescale sales office. © 2011 Freescale Semiconductor, Inc. All rights reserved. Document Number: MPC8358EEC Rev. 3, 01/2011 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 ...
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... MPHY) Figure 1. MPC8358E Block Diagram System Interface Unit (SIU) Memory Controllers GPCM/UPM/SDRAM DDRC 32/64 DDR Interface Unit PCI PCI Bridge Local Local Bus Bus Arbitration DUART Dual I2C 4 Channel DMA Interrupt Controller Protection & Configuration System Reset Clock Synthesizer Freescale Semiconductor ...
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... Ethernet over first mile IEEE 802.3ah – Shim header – Ethernet-to-Ethernet/AAL5/AAL2 inter-working – L2 Ethernet switching using MAC address or IEEE Std. 802.1P/Q™ VLAN tags 1.SMII or SGMII media-independent interface is not currently supported. MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 1 Overview 3 ...
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... Programmable field size up to 511 bits — Data encryption standard execution unit (DEU) – DES, 3DES – Two key (K1, K2) or three key (K1, K2, K3) – ECB and CBC modes for both DES and 3DES MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev Freescale Semiconductor ...
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... SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2 — External driver impedance calibration — On-die termination (ODT) • PCI interface — PCI Specification Revision 2.3 compatible MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor Overview 5 ...
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... External and internal interrupts directed to communication processor — Redirects interrupts to external INTA pin when in core disable mode — Unique vector number for each interrupt source • Dual industry-standard I — Two-wire interface MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev interfaces Freescale Semiconductor ...
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... MPC8358E. The device is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor Electrical Characteristics 2 C-1 EPROM by boot sequencer ...
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... DD 1 Max Value Unit V –0 –0 –0.3 to 2.75 –0.3 to 1.89 –0 –0 –0.3 to ( –0.3 to (GV + 0.3) V REF DD –0.3 to ( –0.3 to ( –0.3 to ( °C –55 to 150 Figure Freescale Semiconductor Notes — — — — — — 2. ...
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... Notes and negative direction. MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor DDR DDR2 2 C, SPI, must track each other and must vary in the same direction—either in the positive or Electrical Characteristics Table 2 Recommended Symbol Unit Value V 1.2 V ± ...
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... Figure 3. Maximum AC Waveforms on PCI interface for 3.3-V Signaling MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev GND Not to Exceed 10 interface refers to the clock period associated with the bus clock interface (Min) +7 (Max (Max) 62.5 ns +3.6 V –3 /OV / 7.1 V p-to-p (Min 7.1 V p-to-p (Min) Freescale Semiconductor ...
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... In the case where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal value before the I/O supplies reach 0.7 V, see MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor Table 3. Output Drive Capability Output Impedance (Ω) ...
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... Frequency (MHz) 266 266 400 , 1 junction temperature 1 process, a junction 0.7 V Time 4. 1 Typical Maximum Unit 2.2 2.3 W 2.4 2.5 W 2.5 2 For I/O power values, see Table 5. = 105°C, and a Dhrystone benchmark J target, and I 105°C, and an artificial smoke test. J Freescale Semiconductor Notes ...
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... This section provides the clock input DC and AC electrical characteristics for the MPC8358E. The rise/fall time on QUICC Engine block input pins should not exceed 5 ns. This should be enforced especially on clock signals. Rise time refers to signal transitions from 10 from 90 MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor ...
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... CLKIN — — Min Max 2 0 –0.3 0.4 IL — ±10 IN — ±10 IN — ±100 IN Table 7 provides the clock input Typical Max Unit — 66.67 MHz — — ns 1.0 2.3 ns — — ±150 ps Freescale Semiconductor Unit V V μA μA μA Notes 1 — ...
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... Table 9. RESET Pins DC Electrical Characteristics Characteristic Input high voltage Input low voltage Input current Output high voltage Output low voltage MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor = 2.5 ± 0.125 mV/ 3.3 V ± 165 mV DD Symbol Min t — G125 t — ...
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... MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev Symbol Condition 3 not relevant for those pins. OH Min 512 — 1 Min Max Unit — 0.4 V Max Unit Notes — PCI_SYNC_IN — CLKIN — PCI_SYNC_IN — PCI_SYNC_IN — PCI_SYNC_IN — CLKIN — PCI_SYNC_IN — — PCI_SYNC_IN Freescale Semiconductor ...
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... SPI (master/slave) UCC through TDM MCC UTOPIA L2 POS-PHY L2 HDLC bus HDLC/transparent MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor Table 11. PLL and DLL Lock Times Min — 7680 Section 22, “Clocking,” NOTE Interface Operating Max Interface Bit ...
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... OL I — VREF Min QUICC Engine Operating 1 Frequency (MHz) 115 (Kbps (typ Max Unit 1.89 V 0.51 × 0.04 V REF – 0.125 V REF μA ±10 — mA — mA μA ±10 Freescale Semiconductor Notes — — — Notes — — 4 — — — ...
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... It is the supply to which far end signal termination is made and is expected equal This rail should track variations in the DC level of MV REF 4. Output leakage is measured with all outputs disabled MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor Symbol Min I — all times. ...
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... V ± 5%. DD Symbol Min V — 0.31 IH REF (typ Min Max Unit — 0 /2, V (peak-to-peak) = 0.2 V. OUT DD OUT (typ Max Unit MV – 0.25 V REF — V Max Unit MV – 0.31 V REF — V Freescale Semiconductor Notes 1 1 Notes — — Notes — — ...
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... Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications for Source At recommended operating conditions with GV 8 Parameter MCK[n] cycle time, (MCK[n]/MCK[n] crossing) Skew between any MCK to ADDR/CMD MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor of (1.8 or 2.5 V) ± 5%. DD Symbol Min t DISKEW 266 MHz – ...
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... MHz t DDKLDX 200 MHz –0.5 × DDKHMP Min Max Unit — ns 2.8 3.5 — ns 2.6 2.8 3.5 — ns 2.8 3.5 — ns 2.7 3.5 –0.75 0.6 ns — ns 1.0 1.2 — ns 1.0 1.2 –0.5 × t – 0.6 + 0.6 ns MCK MCK Freescale Semiconductor Notes ...
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... Figure 6 shows the DDR SDRAM output timing for address skew with respect to any MCK. ADDR/CMD ADDR/CMD Figure 6. Timing Diagram for t MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor Synchronous Mode (continued 2.5 V) ± 5 Symbol Min t – ...
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... MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev Ω Figure 7. DDR AC Test Load DDR ± 0. REF REF 0.5 × GV 0.5 × MCK DDKHAS DDKHCS DDKHAX DDKHCX NOOP DDKHMP t DDKHMH t DDKHDS t DDKLDS DDKHDX Ω DDR2 Unit ± 0. DDKHME t DDKLDX Freescale Semiconductor Notes 1 2 ...
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... The middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are sampled each sixteenth sample. 8 UCC Ethernet Controller: Three-Speed Ethernet, MII Management This section provides the AC and DC electrical characteristics for three-speed, 10/100/1000, and MII management. MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor Symbol ...
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... Section 8.3, “Ethernet Management Interface Electrical Conditions — –4 Min 4 Min OL DD — — — — ≤ V ≤ Min Max Unit Notes 2.97 3. GND 0. –0.3 0.90 V μA — ±10 supply. DD Freescale Semiconductor 1 — — — — — ...
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... R (rise (fall). 2. This symbol is used to represent the external GTX_CLK125 signal and does not follow the original symbol naming convention. MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management Symbol Conditions LV — ...
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... GMII (G) receive (RX) clock. For rise and fall times, the latter convention t GTXR Min Typ Max Unit — 8.0 — — 2.0 — — ns 0.3 — — ns — — 1.0 ns — — 1.0 ns symbolizes GMII receive GRDVKH clock reference (K) RX Freescale Semiconductor Notes — — — — — — for ...
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... For example, the subscript of t MTX used with the appropriate letter: R (rise (fall). MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management t GRX t ...
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... Note that, in general, MRX = 50 Ω Figure 12. AC Test Load t MTXR 1 Min Typ Max — 400 — — 40 — 35 — 65 10.0 — — 10.0 — — 1.0 — 4.0 1.0 — 4.0 symbolizes MII receive MRDVKH clock reference (K) MRX Ω Freescale Semiconductor Unit for ...
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... For example, the subscript of t convention is used with the appropriate letter: R (rise (fall). MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management t MRX ...
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... RMII (RM) reference (X) clock. For rise and fall times, the latter RMX = 50 Ω Figure 15. AC Test Load t RMXR Min Typ Max — 20 — 35 — 65 4.0 — — 2.0 — — 1.0 — 4.0 1.0 — 4.0 symbolizes RMII RMRDVKH RMX Ω Freescale Semiconductor Unit for clock ...
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... TTX letter: R (rise (fall). 2. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention. MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management t RMX ...
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... TRX t TTXR t TTKHDX Min Typ Max Unit — 16.0 — ns 7.5 — 8 — 2.5 — — ns 1.0 — — ns 0.7 — 2.4 ns 0.7 — 2.4 ns symbolizes TBI receive TRDVKH clock reference (K) TRX Freescale Semiconductor Notes — — — — — for ...
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... Duty cycle for 1000Base-T Duty cycle for 10BASE-T and 100BASE-TX Rise time (20–80%) Fall time (20–80%) GTX_CLK125 reference clock period MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management t TRX t t ...
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... UCC2 option 1 and –0.9 for UCC2 option 2, and t RGTH t SKRGTKHDX TXD[8:5] TXD[3:0] TXD[7:4] TXD[4] TXD[9] TXEN TXERR RXD[8:5] RXD[3:0] RXD[7:4] t SKRGTKHDX RXD[9] RXD[4] RXERR RXDV Typ Max Unit Notes — — of the lowest speed transitioned RGT SKRGTKHDX t RGT t SKRGTKHDX t SKRGTKHDX Freescale Semiconductor ...
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... MDC to MDIO delay MDIO to MDC setup time MDIO to MDC hold time MDC rise time MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management Section 8.1, “Three-Speed Ethernet Controller Table 35. ...
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... MDC t t MDCH MDHF t MDRDVKH t MDRDXKH t MDTKHDX Symbol t TMRCK t TMRCKS t TMRCKH t GCLKNV Typ Max Unit — symbolizes management MDKHDX t MDCR Min Max Unit 0 70 MHz — — — — — — Freescale Semiconductor Notes — for Notes — ...
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... LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor Symbol Min Max t — ...
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... LBIXKH1 clock reference (K) goes high (H), in this case for of the signal in question for 3.3 Min Max Unit 15 — — ns 1.0 — ns 1.5 — — ns 2.5 — ns — Freescale Semiconductor Notes — — — for Notes ...
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... DLL bypass mode is not recommended for use at frequencies above 66 MHz. Figure 21 provides the AC test load for the local bus. Output MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor Symbol t LBKHOZ (first two letters of functional block)(signal)(state)(reference)(state) for outputs ...
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... Figure 23. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode) MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev LBIVKH t t LBKHOX LBKHOV t LBKHOZ t t LBKHOX LBKHOV t LBKHOZ t t LBKHOX LBKHOV t LBOTOT t LBKHLR t LBIVKH t LBKHOV t LBKHOZ t LBKHOV t LBOTOT t LBIXKH t LBIXKH t LBIXKH t LBIVKH t LBIXKH t LBIXKH Freescale Semiconductor ...
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... Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) UPM Mode Output Signals: LCS[0:3]/LBS[0:3]/LGPL[0:5] Figure 25. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV (DLL Bypass Mode) MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor t LBKHOZ1 t LBKHOV1 t LBIVKH2 ...
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... Bypass Mode) UPM Mode Output Signals: LCS[0:3]/LBS[0:3]/LGPL[0:5] Figure 26. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV (DLL Bypass Mode) MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev LBKHOZ t LBKHOV t LBIVKH t t LBKHOZ t LBKHOV t LBIXKH t LBIXKH LBIVKH Freescale Semiconductor ...
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... DC electrical characteristics for the IEEE 1149.1 (JTAG) interface of the device. Table 41. JTAG interface DC Electrical Characteristics Characteristic Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor t LBKHOZ1 t LBKHOV1 t LBIVKH2 t LBIVKH1 t ...
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... Note that, in general, JTG . TCLK . TCLK Figure 29 through Figure 32 Min Max Unit 0 33.3 MHz 30 — JTG JTGF 25 — — 4 — — 10 — — 2 — the midpoint of the signal in question. TCLK Figure symbolizes JTAG JTDVKH JTG Freescale Semiconductor Notes — — — — 21). clock ...
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... JTAG External Clock Boundary Data Inputs t JTKLDX Boundary Data Outputs Boundary Output Data Valid Data Outputs MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor = 50 Ω JTKHKL t JTG VM = Midpoint Voltage (OV DD /2) VM ...
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... TDI, TMS t JTKLOX TDO TDO Output Data Valid Figure 32. Test Access Port Timing Diagram MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev JTIVKH Input Data Valid t JTKLOV Output Data Valid t JTKLOZ VM = Midpoint Voltage (OV DD /2) t JTIXKH Freescale Semiconductor ...
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... Setup time for a repeated START condition Hold time (repeated) START condition (after this period, the first clock pulse is generated) Data setup time MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 2 C interface of the device. 2 Table 43 Electrical Characteristics of 3.3 V ± ...
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... DD 0.2 × OV — symbolizes I C timing (I2) I2DVKH clock reference (K) going to the high I2C symbolizes I I2PVKH min of the SCL signal) to bridge the the SCL signal. I2CL Ω I2CF t I2CR t I2PVKH P S Freescale Semiconductor Unit μ μs μ for 2 C clock I2C ...
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... For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. Input timings are measured at the pin. MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor Table 45. PCI DC Electrical Characteristics Symbol Test Condition ≥ ...
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... For example, t symbolizes PCI timing (PC) with respect to the time hard reset PCRHFV = 50 Ω Ω Figure 35. PCI AC Test Load t PCIVKH t PCIXKH Max Unit Notes — — — — — symbolizes PCI timing PCIVKH , reference SYS Freescale Semiconductor ...
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... Timers inputs and outputs are asynchronous to any visible clock. Timers outputs should be synchronized before use by any external synchronous logic. Timers inputs are required to be valid for at least t MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor t PCKHOV ...
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... R L Figure 38. Timers AC Test Load Symbol Condition – — — ≤ V ≤ PIWID Min Max Unit Notes 2.4 — — 0 — –0.3 0.8 V — μA — ±10 — Symbol Typ Unit PIWID ns to ensure proper operation. Freescale Semiconductor ...
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... IPIC inputs are required to be valid for at least t in edge triggered mode. 16 SPI This section describes the DC and AC electrical specifications for the SPI of the MPC8358E. MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor = 50 Ω Figure 39. GPIO AC Test Load Table 52 ...
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... OV — ± Symbol Min Max t 0.4 — NIKHOX t — 8 NIKHOV t 2 — NEKHOX t — 8 NEKHOV t 8 — NIIVKH t 0 — NIIXKH t 4 — NEIVKH t 2 — NEIXKH symbolizes the NMSI NIKHOV Ω Freescale Semiconductor Unit μA Unit for ...
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... DC electrical characteristics for the device TDM/SI. Table 56. TDM/SI DC Electrical Characteristics Characteristic Output high voltage Output low voltage Input high voltage MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor Table 55. Note that although the specifications t NEIXKH t NEKHOV ...
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... TDM/ Ω Ω Figure 43. TDM/SI AC Test Load Table 55. Note that although the specifications generally Min Max Unit –0.3 0.8 — ± Min Max Unit — 2 — symbolizes the TDM/SI SEKHOX Freescale Semiconductor V μ for ...
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... UTOPIA outputs—Internal clock delay UTOPIA outputs—External clock delay UTOPIA outputs—Internal clock high impedance UTOPIA outputs—External clock high impedance UTOPIA inputs—Internal clock input setup time MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor t SEIXKH t SEKHOV t ...
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... UTOPIA = 50 Ω Figure 45. UTOPIA AC Test Load Table 55. Note that although the specifications t UEIXKH t UEKHOV t UEKHOX 1 (continued) Min Max Unit 4.2 — ns 2.4 — — ns symbolizes the UTOPIA UIKHOX Ω Freescale Semiconductor Notes — — — for ...
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... Table 60. HDLC, BISYNC, Transparent, and Synchronous UART DC Electrical Characteristics Characteristic Output high voltage Output low voltage Input high voltage Input low voltage Input current MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor HDLC, BISYNC, Transparent, and Synchronous UART t UIIXKH t UIIVKH t UIKHOV ...
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... Min Max Unit 0 11.2 1 10.8 -0.5 5 8.5 — 4 — 1.4 — 1 — symbolizes the outputs HIKHOX 1 2 Min Max Unit 0 11 — 8 — 1 — 1 — symbolizes the outputs HIKHOX Freescale Semiconductor for for ...
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... Note) Output Signals: (See Note) Note: The clock edge is selectable. Figure 50. AC Timing (Internal Clock) Diagram MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor HDLC, BISYNC, Transparent, and Synchronous UART = 50 Ω Figure 48. AC Test Load ...
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... Max Unit Notes — ns Full speed 48 MHz — ns Low speed 6 MHz 5 ns — Full speed transitions 100 ns Low speed transitions for receive signals symbolizes USB timing (US) for the USRSPND symbolizes USB timing (US) for the USB USTSPN Ω Freescale Semiconductor Unit μA ...
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... Package outline Interconnects Pitch Module height (typical) Solder Balls Ball diameter (typical) MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor Section 21.1, “Package Parameters for the PBGA Package,” for information on the package 668 1. Sn/36 Pb/2 Ag (ZQ package) 95 ...
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... Figure 52. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package Notes: 1. All dimensions are in millimeters. 2. Dimensions and tolerances per ASME Y14.5M-1994. 3. Maximum solder ball diameter measured parallel to datum A. MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev Freescale Semiconductor ...
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... PCI_AD[0:31]/ PG[0:31] PCI_C_BE[0:3]/ PF[7:10] MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor Table 65. MPC8358E PBGA Pinout Listing Package Pin Number DDR SDRAM Memory Controller Interface AD20, AG24, AF24, AH24, AF23, AE22, AH26, AD21, AH25, AD22, AF27, AB24, AG25, AC22, AE25, AC24, ...
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... AG21, AH22, AC20, AD19 AF18 AF10 AC17 AD17 Power Pin Type Notes Supply I/O OV — I/O OV — — — — DD I/O OV — DD I/O OV — DD I/O OV — — — — — — DD I/O OV — DD I/O OV — DD Freescale Semiconductor ...
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... CORE_SRESET IRQ[4:5] IRQ[6:7] UART1_SOUT UART1_SIN UART1_CTS UART1_RTS IIC1_SDA IIC1_SCL IIC2_SDA IIC2_SCL CE_PA[0] MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor Package Pin Number AH19 AE18 AG19 AF19 AD8 AC9 AG6 AE7 AG4 AC8 Programmable Interrupt Controller ...
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... DD I — DD I/O OV — — DD I/O OV — — DD I/O OV — DD I/O OV — — DD I/O OV — — — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — — DD I/O OV — — — — DD Freescale Semiconductor ...
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... HRESET SRESET THERM0 THERM1 GND MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor Package Pin Number AE8 AG7 AH7 AG8 Test AF9 AE27 PMC AF4 System Control AE9 AG9 AH10 Thermal Management K25 AA26 Power and Ground Signals ...
Page 72
... Pin Type Notes Supply Power for GV — DD DDR DRAM I/O Voltage (2 1.8 V) — — DD — — Power for V — DD Core (1.2 V) PCI, OV — DD 10/100 Ethernet, and other Standard (3 DDR — Referenc e Voltage I DDR — Referenc e Voltage — — — DD. Freescale Semiconductor ...
Page 73
... CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (÷2) and the multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor e300 Core Core PLL csb_clk ...
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... DDRC1 memory bus clock outputs (MEMC1_MCK and MEMC1_MCK). However, the data rate is the same frequency as ddr1_clk. The internal lb_clk frequency is determined by the following equation: lb_clk = csb_clk × RCWL[LBCM]) MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev Freescale Semiconductor ...
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... The local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on LCRR[CLKDIV]) which is in turn the csb_clk frequency (depending on RCWL[LBCM]). MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor Table 66 specifies which units have a configurable clock Table 66. Configurable Clock Units ...
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... Table 69. System PLL VCO Divider RCWL[SVCOD] VCO Divider Reserved NOTE Table 68 × 16 × 2 × 3 × 4 × 5 × 6 × 7 × 8 × 9 × 10 × 11 × 12 × 13 × 14 × 15 Table 69 Freescale Semiconductor shows the ...
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... High 0010 High 0011 High 0100 High 0101 MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor the LBCM, DDRCM, and SPMF parameters in the reset Table 70. CSB Frequency Options csb_clk : 16.67 2 Input Clock Ratio 2:1 3:1 4:1 ...
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... Input Clock Frequency (MHz) 16.67 25 33.33 csb_clk Frequency (MHz) 200 233 VCO divider PLL bypassed (PLL off, csb_clk clocks core directly) ÷ 2 ÷ 4 ÷ 8 ÷ 8 ÷ 2 ÷ 4 ÷ 8 Freescale Semiconductor 2 66.67 ...
Page 79
... The QUICC Engine block PLL is controlled by the RCWL[CEPMF], RCWL[CEPDF], and RCWL[CEVCOD] parameters. block PLL. Table 72. QUICC Engine Block PLL Multiplication Factors RCWL[CEPMF] RCWL[CEPDF] 00000 00001 00010 00011 00100 MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor core_clk : csb_clk Ratio 2–5 6 0001 1 1.5:1 0010 0 2:1 ...
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... Multiplication Factor = RCWL[CEPMF RCWL[CEPDF]) 0 × × × × × × × × × × × × × × × × × × × × × × × × × × × × 1.5 1 × 2.5 1 × 3.5 1 × 4.5 Freescale Semiconductor ...
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... The QUICC Engine block VCO frequency is derived from the following equations: ce_clk = (primary clock input × CEPMF) ÷ CEPDF) QE VCO Frequency = ce_clk × VCO divider × CEPDF) MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor QUICC Engine PLL Multiplication Factor = RCWL[CEPMF RCWL[CEPDF]) 1 × ...
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... Freescale Semiconductor 667 (MHz) ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ...
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... Insert the chosen SPMF, COREPLL, CEPMF and CEPDF to the RCWL fields, respectively. CORE SPMF CEPMF PLL 1000 0000011 01001 MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor Input CSB Freq Core Freq CEPDF Clock Freq (MHz) (MHz — ...
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... MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev × where P is the power dissipation of the I/O drivers I/O I/O Symbol Value Unit Notes °C θJA °C θJA °C θJMA R 11 •C/W C θJMA R 6 •C/W C/W 4 θ •C/W C/W 5 θJC ψ 4 •C/W C Freescale Semiconductor ...
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... When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition: the component is soldered to a board with internal planes. MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor , can be obtained from the equation ...
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... Because there is not a standard application environment, a standard heat sink is not required. MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev can be used to determine the junction temperature with For instance, the user can change the size of the heat θ CA Freescale Semiconductor ...
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... Internet: www.alphanovatech.com International Electronic Research Corporation (IERC) 413 North Moss St. Burbank, CA 91502 Internet: www.ctscorp.com MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor Natural Convection Natural Convection 25 mm Pin Fin Natural Convection 25 mm Pin Fin 25 mm Pin Fin ...
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... If an adhesive attachment is planned, the adhesive should be intended for attachment to painted or plastic surfaces and its performance verified under the application requirements. MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev 408-436-8770 800-522-6752 603-635-5102 781-935-4850 800-248-2481 888-642-7674 800-347-4572 Freescale Semiconductor ...
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... PLL, the opportunity to cause noise injection from one PLL to the other is reduced. MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor ) D 1) generates the platform clock from the externally supplied CLKIN Section 22.1, “ ...
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... Low ESL Surface Mount Capacitors GND Figure 54. PLL Power Supply Filter Circuit , and LV planes, to enable quick recharging of the smaller chip pin being supplied to minimize and LV pins of the device. These and GND required. Unused active high and GND pins Freescale Semiconductor DD ...
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... The driver impedance are targeted at minimum V nominal OV , 105°C. DD Local Bus, Ethernet, DUART, Impedance Control, Configuration, Power Management MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 2 C). is trimmed until the voltage at the pad equals P )/ Pad Data R ...
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... For available frequencies, contact your local Freescale sales office. In addition to the processor frequency, the part numbering scheme also MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev PCI 105°C. J DDR DRAM Symbol Unit DIFF Freescale Semiconductor ...
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... Additionally, parts addressed by part number specifications may support other maximum core frequencies. Table 79 shows the SVR settings by device and package type. MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor Table 78. Part Numbering Nomenclature ...
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... OCCR[PCICDn] parameters select whether CLKIN Configuration,” updated the system VCO frequency conditions. Section 23.2.4, “Heat Sinks and 76, “Heat Sinks and Junction-to-Ambient Thermal 1 ,” added row for 400/266/400 part offering. . I2DVKH Table 78, “Part Numbering Characteristics.” Freescale Semiconductor ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...