MPC8358EZQAGDGA Freescale Semiconductor, MPC8358EZQAGDGA Datasheet - Page 90

• Manufacturer Part Number: MPC8358EZQAGDGA
• Description: MPU POWERQUICC II PRO 668-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8358EZQAGDGA

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 668-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

System Design Information
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AV
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV
pin, which is on the periphery of package, without the inductance of vias.
Figure 54
24.3
Due to large address and data buses as well as high operating frequencies, the device can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the device system, and the device itself
requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer
place at least one decoupling capacitor at each V
decoupling capacitors should receive their power from separate V
power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly
under the device using a standard escape pattern. Others may surround the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the V
capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the
quick response time necessary. They should also be connected to the power and ground planes through two
vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo
OSCON).
24.4
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to OV
inputs should be connected to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external V
the device.
90
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
Connection Recommendations
Decoupling Recommendations
shows the PLL power supply filter circuit.
DD
, OV
V
DD
DD
, GV
DD
Figure 54. PLL Power Supply Filter Circuit
, and LV
10 Ω
DD
2.2 µF
planes, to enable quick recharging of the smaller chip
DD
GND
, OV
DD
Low ESL Surface Mount Capacitors
, GV
DD
2.2 µF
, GV
DD
DD
, or LV
, GV
DD
DD
, and LV
DD
AV
, OV
DD
DD
DD
pin being supplied to minimize
, LV
n
as required. Unused active high
DD
DD
DD
, GV
, OV
pins of the device. These
DD
DD
Freescale Semiconductor
, LV
, and GND pins of
DD
, and GND
DD