MC68030CRC25C Freescale Semiconductor, MC68030CRC25C Datasheet - Page 131

• Manufacturer Part Number: MC68030CRC25C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

5
5.6.7
5.6.8 Data Transfer and Size Acknowledge (DSACK0, DSACK1)
5.6.9 Synchronous Termination (STERM)
5.6.6
5-6
This output is an enable signal for external data buffers. This signal may not
should place valid data on the data bus. During a write cycle, the data strobe
clock synchronous write cycles, the MC68030 does not assert DS. Refer to
7.1.5
operation.
a system that supports two-clock synchronous bus cycles. Refer to 7.1.6
Buffer Enable
operation.
These inputs indicate the completion of a requested data transfer operation.
of each cycle. These signals apply only to asynchronous bus cycles. Refer to
7.1.7
and their relationship to dynamic bus sizing.
This input is a bus handshake signal indicating that the addressed port size
is 32 bits and that data is to be latched on the next falling clock edge for a
of STERM to bus operation.
During a read cycle, this three-state output indicates that an external device
indicates that the MC68030 has placed valid data on the bus. During two-
be required in all systems. The timing of this signal may preclude its use in
In addition, they indicate the size of the external bus port at the completion
read cycle. This signal applies only to synchronous operation. Refer to 7.1.7
Bus Cycle Termination Signals
Data Buffer Enable (DBEN)
Data Strobe (DS)
Data Strobe
Bus Cycle Termination
for more information about the relationship of DBEI~ to bus
for more information about the relationship of DS to bus
MC68030 USER'S MANUAL
Signals for more information on these signals
for more information about the relationship
MOTOROLA
Data