MC68030CRC25C Freescale Semiconductor, MC68030CRC25C Datasheet - Page 488

• Manufacturer Part Number: MC68030CRC25C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

MOTOROLA
The instruction-cache-case and average no-cache-case columns of the in-
the given cache case and instruction. The first number inside the parentheses
word-aligned case and the even-word-aligned case (rounded up toan integral
within the parentheses is the number of write cycles performed by the in-
The total numbers of bus-activity clocks and internal clocks (not overlapped
The example used here is taken from a no-cache-case 'fetch effective address'
time. The addressing mode is
that are not included in the corresponding instruction timings. These cases
struction timing tables contain four sets of numbers, three of which are
enclosed in parentheses. The outer number is the total number of clocks for
second value inside the parentheses is the maximum number of instruction
instruction pipe filled. Because the second value is the average of the odd-
of bus cycles (one bus cycle per two instruction prefetches). The third value
struction. One example from the instruction timing table is:
by bus activity) of the instruction in this example are derived as follows:
instruction-cache-case execution time, no instruction accesses are required
because the cache is enabled and the sequencer does not have to access
external memory for the instruction words.
The first five timing tables deal exclusively with fetching and calculating
effective addresses and immediate operands. The remaining tables are in-
struction and operation timings. Some instructions use addressing modes
calculation. All read and write accesses are assumed to take two clock periods.
is the number of operand read cycles performed by the instruction. The
bus cycles performed by the instruction, including all prefetches to keep the
number of bus cycles), it is always greater than or equal to the actual number
under the instruction-cache-case execution time entry is 18(2/0/0). For the
refer to footnotes that indicate the additional table needed for the timing
Maximum Number of Instructio~ Access Cycles
(2 Readso2 Clocks/Read)+ (3 Instruction Accesses°2 Clocks/Access)+
21 Total Clocks-10 Bus Activity Clocks= 11 Internal Clocks
(0 Writes*2 Clocks/Write)-10 Clocks of Bus Activity
Number of Writes Cycles
MC68030 USER'S MANUAL
Total Number of Clocks
Number of Read Cycles
([d32,B],l,d32).
The same addressing mode
21 (2 / 3 / O)
11-25
11