IP-NIOS Altera, IP-NIOS Datasheet - Page 40

• Manufacturer Part Number: IP-NIOS
• Description: IP NIOS II MEGACORE
• Manufacturer: Altera
• Type: Licenser

Specifications of IP-NIOS

• Processor Type: RISC 32-Bit
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• Features: -
• Package / Case: -
• Mounting Type: -
• Voltage: -
• Speed: -

2–18
JTAG Debug Module
Nios II Processor Reference Handbook
f
f
1
For further details on the MPU implementation, refer to the
chapter of the Nios II Processor Reference Handbook.
You can optionally include the MPU when you instantiate the Nios II processor in
your Nios II hardware system. When present, the MPU is always enabled. Several
parameters are available, allowing you to optimize the MPU for your system needs.
For complete details of user-selectable parameters for the Nios II MPU, refer to the
Instantiating the Nios II Processor in SOPC Builder
Reference Handbook.
The Nios II MPU is optional and mutually exclusive from the Nios II MMU. Nios II
systems can include either an MPU or MMU, but cannot include both an MPU and
MMU on the same Nios II processor core.
The Nios II architecture supports a JTAG debug module that provides on-chip
emulation features to control the processor remotely from a host PC. PC-based
software debugging tools communicate with the JTAG debug module and provide
facilities, such as the following features:
■
■
■
■
■
The debug module connects to the JTAG circuitry in an Altera FPGA. External
debugging probes can then access the processor via the standard JTAG interface on
the FPGA. On the processor side, the debug module connects to signals inside the
processor core. The debug module has nonmaskable control over the processor, and
does not require a software stub linked into the application under test. All system
resources visible to the processor in supervisor mode are available to the debug
module. For trace data collection, the debug module stores trace data in memory
either on-chip or in the debug probe.
The debug module gains control of the processor either by asserting a hardware break
signal, or by writing a break instruction into program memory to be executed. In both
cases, the processor transfers execution to the routine located at the break address.
The break address is specified in SOPC Builder at system generation time.
Soft-core processors such as the Nios II processor offer unique debug capabilities
beyond the features of traditional, fixed processors. The soft-core nature of the Nios II
processor allows you to debug a system in development using a full-featured debug
core, and later remove the debug features to conserve logic resources. For the release
version of a product, the JTAG debug module functionality can be reduced, or
removed altogether.
Downloading programs to memory
Starting and stopping execution
Setting breakpoints and watchpoints
Analyzing registers and memory
Collecting real-time execution trace data
1
The Nios II MMU does not support the JTAG debug module trace.
chapter of the Nios II Processor
December 2010 Altera Corporation
Chapter 2: Processor Architecture
Programming Model
JTAG Debug Module