IP-NIOS Altera, IP-NIOS Datasheet - Page 123

• Manufacturer Part Number: IP-NIOS
• Description: IP NIOS II MEGACORE
• Manufacturer: Altera
• Type: Licenser

Specifications of IP-NIOS

• Processor Type: RISC 32-Bit
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• Features: -
• Package / Case: -
• Mounting Type: -
• Voltage: -
• Speed: -

Chapter 4: Instantiating the Nios II Processor in SOPC Builder
JTAG Debug Module Page
Figure 4–5. JTAG Debug Module Page in the Nios II Processor Parameter Editor
Table 4–2. JTAG Debug Module Levels (Part 1 of 2)
December 2010 Altera Corporation
Logic Usage
On-Chip Memory Usage
Debug Feature
Debug Level Settings
f
There are five debug levels available in the JTAG Debug Module page, as shown in
Figure
Table 4–2
consume different amounts of on-chip resources. Certain Nios II cores have restricted
debug options, and certain options require debug tools provided by First Silicon
Solutions (FS2) or Lauterbach GmbH.
For details on debug features available from these third parties, refer to the FS2
website (www.fs2.com) and the Lauterbach GmbH website (www.lauterbach.com).
4–5.
is a detailed list of the characteristics of each debug level. Different levels
No Debug
0
0
300—400 LEs
Two M4Ks
Level 1
800—900 LEs 2,400—2,700 LEs 3,100—3,700 LEs
Two M4Ks
Level 2
Four M4Ks
Level 3
Nios II Processor Reference Handbook
Level 4
Four M4Ks
(1)
4–15