IP-NIOS Altera, IP-NIOS Datasheet - Page 183

• Manufacturer Part Number: IP-NIOS
• Description: IP NIOS II MEGACORE
• Manufacturer: Altera
• Type: Licenser

Specifications of IP-NIOS

• Processor Type: RISC 32-Bit
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• Features: -
• Package / Case: -
• Mounting Type: -
• Voltage: -
• Speed: -

Chapter 7: Application Binary Interface
ABI for Linux Systems
December 2010 Altera Corporation
Procedure Linkage Table
Function calls in a position-dependent executable may use the call and jmpi
instructions, which address the contents of a 256 MB segment. They may also use the
%lo, %hi, and %hiadj operators to take the address of a function. If the function is in
another shared object, the link editor creates a callable stub in the executable called a
PLT entry. The PLT entry loads the address of the called function from the PLT GOT (a
region at the start of the GOT) and transfers control to it.
The PLT GOT entry needs a relocation referring to the final symbol, of type
R_NIOS2_JUMP_SLOT. The dynamic linker may immediately resolve it, or may leave
it unmodified for lazy binding. The link editor fills in an initial value pointing to the
lazy binding stubs at the start of the PLT section.
Each PLT entry appears as shown in
Example 7–18. PLT Entry
.PLTn:
Example 7–19
data area for a relative jump.
Example 7–19. PLT Entry Near Small Data Area
.PLTn:
Example 7–20
Example 7–20. Initial PLT Entry
res_0:
.PLTresolve:
In front of the initial PLT entry, a series of branches start of the initial entry (the nextpc
instruction). There is one branch for each PLT entry, labelled res_0 through res_N. The
last several branches may be replaced by nop instructions to improve performance.
The link editor arranges for the Nth PLT entry to point to the Nth branch, res_N –
res_0 is four times the index into the .rela.plt section for the corresonding
R_JUMP_SLOT relocation.
orhi
ldw
jmp
ldw
jmp
br
...
orhi
addi
sub
orhi
ldw
ldw
jmp
r15, r0, %hiadj(plt_got_slot_address)
r15, %lo(plt_got_slot_address)(r15)
r15
r15, %gprel(plt_got_slot_address)(gp)
r15
.PLTresolve
r14, r0, %hiadj(res_0)
r14, r14, %lo(res_0)
r15, r15, r14
r13, %hiadj(_GLOBAL_OFFSET_TABLE_)
r14, %lo(_GLOBAL_OFFSET_TABLE_+4)(r13)
r13, %lo(_GLOBAL_OFFSET_TABLE_+8)(r13)
r13
shows the PLT entry when the PLT GOT is close enough to the small
shows the initial PLT entry.
Example
7–18.
Nios II Processor Reference Handbook
7–19