IP-NIOS Altera, IP-NIOS Datasheet - Page 280

• Manufacturer Part Number: IP-NIOS
• Description: IP NIOS II MEGACORE
• Manufacturer: Altera
• Type: Licenser

Specifications of IP-NIOS

• Processor Type: RISC 32-Bit
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• Features: -
• Package / Case: -
• Mounting Type: -
• Voltage: -
• Speed: -

8–94
sth / sthio
Nios II Processor Reference Handbook
Operation:
Assembler Syntax:
Example:
Description:
Usage:
Exceptions:
Instruction Type:
Instruction Fields:
31
31
30
30
29
29
A
A
28
28
27
27
26
26
25
25
24
24
B
B
Mem16[rA + σ (IMM16)] ← rB
sth rB, byte_offset(rA)
sthio rB, byte_offset(rA)
sth r6, 100(r5)
Computes the effective byte address specified by the sum of rA and the instruction's signed
16-bit immediate value. Stores the low halfword of rB to the memory location specified by the
effective byte address. The effective byte address must be halfword aligned. If the byte address
is not a multiple of 2, the operation is undefined.
In processors with a data cache, this instruction may not generate an Avalon-MM data transfer
immediately. Use the sthio instruction for peripheral I/O. In processors with a data cache,
sthio bypasses the cache and is guaranteed to generate an Avalon-MM data transfer. In
processors without a data cache, sthio acts like sth.
Supervisor-only data address
Misaligned data address
TLB permission violation (write)
Fast TLB miss (data)
Double TLB miss (data)
MPU region violation (data)
I
A = Register index of operand rA
B = Register index of operand rB
IMM16 = 16-bit signed immediate value
23
23
22
22
21
21
20
20
19
19
Instruction format for sthio
Instruction format for sth
18
18
17
17
16
16
15..0
15
15
store halfword to memory or I/O peripheral
IMM16
IMM16
14
14
13
13
12
12
11
11
10
10
9
9
8
8
Chapter 8: Instruction Set Reference
December 2010 Altera Corporation
7
7
6
6
5
5
Instruction Set Reference
4
4
0x0d
0x2d
3
3
2
2
1
1
0
0