DP8344BV National Semiconductor, DP8344BV Datasheet - Page 168

• Manufacturer Part Number: DP8344BV
• Description: IC BIPHASE COMM PROCESSR 84-PLCC
• Manufacturer: National Semiconductor

Specifications of DP8344BV

• Processor Type: 8-Bit RISC
• Speed: 20MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: *DP8344BV

6 0 Reference Section
IBR INTERRUPT BASE REGISTER
IV15 –8
The interrupt vector is obtained by concatenating
with the vector address
Alternate R1 read write
15
IV15
NMI
Receiver
Transmitter
Line Turn Around
Bi-directional
Timer
7
Interrupt
IV14
Interrupt Vector
trap vectors Further information Section 2 2 3
Interrupts
6
IBR
IV13
5
Interrupt Vector
IV12
Vector Address
4
8
0 1 1 1 0 0
0 0 0 1 0 0
0 0 1 0 0 0
0 0 1 1 0 0
0 1 0 0 0 0
0 1 0 1 0 0
0
IV11
3
High byte of interrupt and
0
(Continued)
5
IV10
2
vector address
IV9
1
Priority
1 high
2
3
4
5 low
IV8
IBR
0
0
168
ICR INTERRUPT CONTROL REGISTER
rsv
RIS1 0
IM4–0
Main R2 read write
RIS1
7
state is undefined at all times
RIS0
Receiver Interrupt Select
source of the Receiver Interrupt
Further information Section 3 2 3 Transceiver In-
terrupts
Interrupt Masks
masks an interrupt IM3 functions as an interrupt
mask only if BIRQ is defined as an input When
BIRQ is defined as an output IM3 controls the
state of BIRQ
Further information Section 2 2 3 Interrupts
6
X X X X 1 Receiver
X X X 1 X Transmitter
X X 1 X X Line Turn-Around
X 1 X X X Bi-Directional
1 X X X X Timer
0 0 0 0 0
‘‘
IM4– 0
RIS1 0 Interrupt Source
rsv
a
5
0 0
0 1
1 0
1 1
’’ indicates logical ‘‘or’’
IM4
RFF
DAV
(unused)
RA
4
No Mask
a
a
Interrupt
IM3
3
RE
RE
Each bit when set high
IM2
2
IM1
Defines the
1
IM0
0