DP8344BV National Semiconductor, DP8344BV Datasheet - Page 63

• Manufacturer Part Number: DP8344BV
• Description: IC BIPHASE COMM PROCESSR 84-PLCC
• Manufacturer: National Semiconductor

Specifications of DP8344BV

• Processor Type: 8-Bit RISC
• Speed: 20MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: *DP8344BV

4 0 Remote Interface and Arbitration System (RIAS)
4 1 1 Remote Arbitration Phases
The BCP CPU and RIAS share the internal CPU-CLK This
clock is derived from the X1 crystal input It can be divided
by two by setting CCS
setting CCS
Processor is run need not bear any relationship to the CPU-
CLK A remote access is treated as an asynchronous event
and data is handshaked between the Remote Processor
and the BCP
CMD
LCL
LOCK
RAE
REM-RD
REM-WR
WR-PEND
XACK
WAIT
BIS SS FBW LR LW STRT MS1 MS0 RIC
7
Signal
FIGURE 4-2 Remote Interface Control Register
BIS
SS
FBW
LR
LW
STRT
MS1–0
6
5
e
Bidirectional Interrupt Status
Single-Step
Fast Buffered Write mode
Latched Read mode
Latched Write mode
BCP CPU start stop
Memory Selection
0 The frequency at which the Remote
In Out
4
Out
Out
Out
In
In
In
In
In
In
3
e
1 in DCR or run undivided by
2
Pin
45
31
44
46
47
48
49
50
54
1
TABLE 4-1 RIAS Inputs and Outputs
Reset
0
State
X
0
X
X
X
X
1
1
X
CoMmanD input When high remote accesses are directed to the
Remote Interface Configuration register RIC When low remote
accesses are directed to Data Memory Instruction Memory or the
Program Counter as determined by RIC 1 0
LoCaL Normally low goes high when the BCP relinquishes the data
and address bus to service a remote access
Asserting this input Low will LOCK out local (BCP) accesses to Data
Memory Once the remote processor has been granted the bus
LOCK gives it sole access to the bus and BCP accesses are
‘‘waited’’
Remote Access Enable Setting this input low allows host access of
BCP functions and memory
REMote ReaD When low along with RAE a remote read cycle is
requested serviced by the BCP when the data bus becomes
available
REMote WRite When low along with RAE a remote write cycle is
requested serviced by the BCP when the data bus becomes
available
WRite PENDing In a system configuration where remote write
cycles are latched WR-PEND will go low indicating that the latches
contain valid data which have yet to be serviced by the BCP
Transfer ACKnowledge Normally high goes low on REM-RD or
REM-WR going low (if RAE low) returning high when the transfer is
complete Normally used as a ‘‘wait’’ signal to a remote processor
(In the Latched Write mode XACK will only transition if a second
remote access begins before the first one completes )
Asserting this input low will add wait states to both remote accesses
and to the BCP instruction cycle WAIT will extend a remote access
until it is set high
63
The two key handshake signals involved in the BCP RP
interface are Transfer Acknowledge (XACK) and Local
(LCL) Internally two more signals control the access tim-
ing INT-READ and INT-WRITE The timing for a generic
Remote Access is shown in Figure 4-3 A remote access is
initiated by the RP asserting REM-RD or REM-WR with RAE
low There is no set-up hold time relationship between RAE
and REM-RD or REM-WR These signals are internally gat-
ed together such that if RAE (REM-RD
a remote access will begin A short delay later XACK will
fall This signal can be fed back to the RP’s wait line to
extend its read or write cycle if necessary When the BCP’s
FIGURE 4-3 Generic Remote Access (RAE
(Continued)
Function
a
REM-WR) is true
TL F 9336 – 20
e
0)