DP8344BV National Semiconductor, DP8344BV Datasheet - Page 78

• Manufacturer Part Number: DP8344BV
• Description: IC BIPHASE COMM PROCESSR 84-PLCC
• Manufacturer: National Semiconductor

Specifications of DP8344BV

• Processor Type: 8-Bit RISC
• Speed: 20MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: *DP8344BV

4 0 Remote Interface and Arbitration System (RIAS)
On the next clock the state machine will enter RS
will return low The A bus (and AD bus if the access is to
data memory) remains in TRI-STATE for the first half
T-state of RS
mote Processor is no longer using the buses and the BCP
CPU will be granted the buses if LCL-BREQ is asserted If a
local bus request is made a local bus grant will be given to
the Timing Control Unit If the preceding access was a read
of IMEM then HIB is switched and if the access was to the
high byte of IMEM then the PC is incremented If RAE
REM-RD is deasserted at this point the next clock will bring
RASM back to RS
Access is initiated RS
true RASM will loop in RS
active at which time the state machine will return to RS
In Figure 4-17 the BCP is executing the first of two Data
Memory reads when REM-RD goes low In response XACK
goes low waiting the Remote Processor At the end of the
first instruction although the BCP begins its second write by
taking ALE high the RASM now takes control of the bus
and deasserts LCL high at the end of T
delay is built into this transfer to ensure that READ has been
deasserted high before the data bus is switched The Timing
Control Unit is now waited inserting remote access wait
states T
The remote address is permitted one T-state to settle on the
BCP address bus before READ goes low XACK then re-
turns high one T-state plus the programmed Data Memory
wait state T
time READ returns high a half T-state later ensuring suffi-
cient hold time followed by LCL being reasserted low after
an additional half T-state transferring bus control back to
the BCP The Remote Processor responds to XACK return-
ing high by deasserting REM-RD high although by this time
the BCP is well into its own memory read
4 2 3 Slow Buffered Write
The timing for this mode is the same as the Buffered Read
mode The complete flow chart for the Slow Buffered Write
mode is shown in Figure 4-18 Until a Remote Write is initiat-
ed (RAE REM-WR true) the state machine (RASM) loops
in state RS
high RASM will move to state RS
Write is initiated while the buses have been granted locally
(i e Local Bus Grant
The state machine will loop in state RS
is set high or the buses are granted locally If the BCP CPU
needs to access Data Memory while in either RS
(and LOCK is high) it can still do so A local access is re-
quested by the Timing Control Unit asserting the Local Bus
Request (LCL-BREQ) signal A local bus grant will be given
by RASM if the buses are not being used (as is the case in
the RS
XACK is taken low as soon as RAE REM-WR is true re-
gardless of an ongoing local access RASM will move into
RS
there is no local bus request and LOR
local bus requests will be granted until the remote access is
complete and RASM returns to RS
ates a Data Memory access after RS
Unit will be waited and the BCP CPU will remain in state T
until completion of the remote access Half a T-state after
entering RS
On the next CPU-CLK RASM enters RS
high while XACK remains low The wait state counters i
B
on the next clock after RAE REM-WR is asserted and
A
Wr
state)
A1
B
as RASM takes over
Wd
the A and AD buses go into TRI-STATE
If a Remote Write is initiated and LOR is set
F
later having satisfied the memory access
A
After the first half of RS
where it will loop until another Remote
e
G
1) RASM will move to state RS
is entered if RAE REM-RD is still
G
until RAE REM-RD is no longer
A2
A
Likewise if a Remote
A
If the BCP CPU initi-
A2
C
the Timing Control
as long as LOR
1
and LCL is taken
e
A one T-state
0 No further
F
F
and LCL
the Re-
A
state
A
A2
Wr
IW
78
and i
0 respectively in DCR The A and AD buses now remain
in TRI-STATE and the Access Phase begins If the Remote
Access is to IMEM and the high instruction byte flag is set
(i e HIB
machine can move into one of several states depending on
the state of CMD and MS1 –0 on the next clock XACK
remains low and LCL remains high in all the possible next
states If CMD is high the access is to RIC and the next
state will be RS
state Any remote access mode changes made by this write
will not take effect until one T-state after the completion of
the present write
The five other next states all have CMD low and depend on
the Memory Select bits If MS1–0 is 10 or 11 the state
machine will enter either RS
bytes of the Program Counter respectively will be written
and moves RASM into RS
state and A and AD continue to be tri-stated This allows the
Remote Processor to drive the Data Memory address and
data buses for the write Since DMEM is subject to wait
states RS
memory wait states have been inserted
The last possible Memory Selection is Instruction Memory
pend on whether RASM is expecting the low byte or high
byte Instruction words are accessed low byte then high
byte and RASM powers up expecting the low Instruction
byte The internal flag that keeps track of the next expected
Instruction byte is called the High Instruction Byte flag (HIB)
If HIB is low the next state is RS
byte is written into the holding register ILAT If HIB is high
the high instruction byte is moved to I15– 8 and the value in
ILAT is moved to I7– 0 At the same time IWR is asserted
low beginning the write to instruction memory An IMEM
access like a DMEM access is subject to wait states and
these states will be looped on until all programmed Instruc-
tion Memory wait states have been inserted
Note Resetting the BCP will reset HIB (i e HIB
After all of the programmed wait states are inserted in the
RS
WAIT low a half T-state before the end of the last pro-
grammed wait state If there are no programmed wait
states WAIT must be asserted low a half T-state before the
end of RS
remote access is extended indefinitely All the RS
move to their corresponding RS
after the programmed wait state conditions are met and
WAIT is high The RS
REM-WR is deasserted LCL remains high in all RS
but XACK is taken back high to indicate that the remote
access can be terminated If XACK is connected to a Re-
mote Processor wait pin it can now terminate its write cycle
This state begins the Termination Phase The action speci-
fied in the conditional box is only executed while RAE REM-
WR is asserted a clock edge is not necessary
On the CPU-CLK after RAE REM-WR is deasserted RASM
enters RS
buses are still in TRI-STATE The next CPU-CLK causes
RASM to move to RS
MS1–0 equal to 00 designates a Data Memory access
MS1– 0
D
DW
states more wait states may be added by asserting
Memory Select bits in RIC (i e
will also force HIB to zero This way the instruction word boundary
can be reset without resetting the BCP
are loaded in this state from IW1–0 and DW2 –
e
e
F
D4
D
where LCL remains high and the BCP A and AD
1) then IWR is asserted low in RS
01 The two possible next states for IMEM de-
to add wait states If WAIT remains low the
is looped upon until all the programmed data
D1
The path from AD to RIC opens in this
(Continued)
E
A3
states are looped upon until RAE
D4
If the access was to IMEM then
D2
WRITE will be asserted in this
or RS
MS1–0
E
D5
states on the CPU-CLK
and the low instruction
D3
and the low or high
e
e
01 pointing to IMEM)
0) Writing 01 to the
C
The state
E
D
states
states