MMA8205EGR2 Freescale Semiconductor, MMA8205EGR2 Datasheet
MMA8205EGR2
Specifications of MMA8205EGR2
Related parts for MMA8205EGR2
MMA8205EGR2 Summary of contents
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... DSI 2.0 Compliant • Z-axis transducer is overdamped Typical Applications • Crash detection (Airbag) • Impact and vibration monitoring • Shock detection. © Freescale Semiconductor, Inc., 2009, 2010. All rights reserved. Document Number: MMA81XXEG Rev 5, 04/2010 MMA81XXEG MMA82XXEG MMA82XXTEG SERIES SINGLE-AXIS DSI 2.0 ACCELEROMETER ...
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... Tubes 475-01 Tape & Reel 475-01 Tubes 475-01 Tape & Reel 475-01 Tubes 475-01 Tape & Reel 475-01 Tubes 475-01 Tape & Reel 475-01 Tubes 475-01 Tape & Reel 475-01 Tubes 475-01 Tape & Reel 475-01 Tubes Sensors Freescale Semiconductor ...
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... BUSRTN BANDGAP REFERENCE OSCILLATOR SELFTEST TRIM OSC TRIM SELFTEST VOLTAGE C-TO-V g-CELL CONVERTER GAIN TRIM Sensors Freescale Semiconductor REGULATOR REGULATOR LOGIC COMMAND DECODE STATE MACHINE RESPONSE GENERATION SELF-TEST ENABLE A-TO-D CONVERTER LOW-PASS FILTER OFFSET TCS TRIM TRIM Figure 1-1. Overall Block Diagram ...
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... N REG V /TEST FIL D 6 OUT GND IN CLK 8 16-PIN SOIC PACKAGE ACTIVIATION OF X-AXIS SELF-TEST CAUSES OUTPUT TO PROJECTION BECOME MORE POSITIVE + Figure 1-2. Device Pinout BUSRTN 13 BUSIN -X 12 BUSOUT 11 H CAP REG CASE: 475-01 N/C: NO INTERNAL CONNECTION 0 g Sensors Freescale Semiconductor ...
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... ESR Figure 1-3. Voltage Regulator Capacitance and Series Resistance Sensors Freescale Semiconductor is restored to operating levels and the device has undergone post-reset CAP pin for stability. This should be a high grade capacitor SS pins are connected to the external capacitor(s) for best system ...
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... Leave unconnected OUT ) IN /D and measures resulting voltage. This determines the resistance between V IN Figure 1-5. /D GND /D connection options are illustrated in GND IN Figure 1-5 is RIN ≥ 1 MΩ must be directly connected to BUSRTN if the IN Figure 1-5. is continuously monitored. An GND Sensors Freescale Semiconductor / GND ...
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... Thirty-two OTP bits are factory-programmed with a unique serial number during the manufacturing and test. Five additional bits are factory-programmed to indicate the full-scale range and axis of sensitivity. Device identification data may be read at any time while the device is active. Sensors Freescale Semiconductor GROUND-LOSS DETECTION ENABLED (SINGLE-ENDED SYSTEMS ONLY) MMA81XXEG/MMA82XXEG/MMA82XXTEG ...
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... Undervoltage (U) flag set, short-word Read Acceleration Data response value equals zero Accelerometer Status (S) flag set, short-word Read Acceleration Data response value equals zero Accelerometer Status (S) and Ground Fault (GF) flags set, short-word Read Acceleration Data response value equals zero Device Behavior Sensors Freescale Semiconductor ...
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... STDIS U The signal STDIS in Figure 2-1 is set when self-test lockout is activated through the execution of two consecutive Disable Self- Test Stimulus commands, as described in on reset is required to clear a fault condition which results in reset of the D flip-flop. Sensors Freescale Semiconductor TRANSIENT UNDERVOLTAGE CONDITION DEVICE DISABLE BIT, DEVCFG2[4] ...
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... DDIS Customer Defined Customer Defined Customer Defined Customer Defined Customer Defined Customer Defined Customer Defined Customer Defined TO DIGITAL INTERFACE S11 S10 S9 S16 S19 S18 S17 S24 S27 S26 S25 RNG0 0 RNG2 RNG1 AT0 AT1 AD0 AD3 AD2 AD1 Sensors Freescale Semiconductor ...
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... Full-Scale Range Bits (RNG2 - RNG0) These three bits define the calibrated range of the device as follows: RNG2 Sensors Freescale Semiconductor Table 3-2 Serial Number Assignment Bit Range Content S12 - S0 Serial Number S31 - S13 Lot Number Table 3-3 Device Type Register Bit Function 6 5 ...
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... When this bit is programmed to a logic ‘1’ value, ground loss errors will be reported if a ground fault condition is detected Ground-loss detection circuitry enabled 0 - Ground-loss detection disabled. MMA81XXEG 12 Table 3-5 Device Configuration Byte 1 Bit Function Customer Defined Table 3-6 Device Configuration Byte 2 Bit Function PAR2 GLDE DDIS ATT1 ATT0 Section AD3 AD2 AD1 AD0 Sensors Freescale Semiconductor 4. ...
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... Two different methods of programming the eighty customer defined bits are supported. In test mode, these may be programmed in the same manner as factory programmed OTP bits. Additionally, the Read Write NVM DSI bus command may be used. Test mode programming operations are described in Section 4.6.3. Sensors Freescale Semiconductor Appendix A.3. Read Write NVM command operation is described in MMA81XXEG 13 ...
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... RD3 RD2 RD1 FA1 FA0 FD3 FD2 FD1 RA3 RA2 RA1 — — — — — — — — — — Not Applicable B1 B0 PA3 PA2 PA1 Sensors Freescale Semiconductor D0 PA0 — — — — RD0 FD0 RA0 — — PA0 ...
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... Legend: AT1 - AT0: Attribute codes (see Section NV: State of fuse program control bit BS: State of Bus Switch (0: open, 1: closed) S: Accelerometer status flag (1: internal error) ST: Self-Test flag (1: self-test active Undervoltage condition V2 - V0: Version ID Sensors Freescale Semiconductor Table 4-2 Short-Word Response Summary Response Not Applicable NV U ...
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... RA3 RA2 RA1 RA0 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 Response 4.5.1.3) Section PA3 PA2 PA1 PA0 AT1 AT0 See Section 4.6.3 R/W FA2 FA1 FA0 FD3 FD2 FD1 FD0 AT1 AT0 AT1 AT0 PA3 PA2 PA1 PA0 Sensors Freescale Semiconductor 4. ...
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... Format Register Data (FD3 - FD0) Contents of a format control register. This is the data to be written to the register by a Format Control command, or the contents read from the register in response to a Format Control command. Sensors Freescale Semiconductor Table 4-4 Attribute Code Bit Assignments DEVGFG1[1] DEVGFG1[0] ...
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... This bit indicates whether internal self-test stimulus circuitry is active in response to Request Status, Disable Self-Test Stimulus and Activate Self-Test Stimulus commands Self-Test stimulus active 0 - Self-Test stimulus disabled 4.5.1.17 Undervoltage Flag (U) This flag is set if the voltage at HCAP is below a specified threshold. Refer to MMA81XXEG 18 Section 1.3.1 and Section 5 for further details. Freescale Semiconductor Sensors ...
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... Both fields will contain the value PA3 - PA0 to indicate successful device address assignment. Initialization or reverse initialization commands which attempt to assign device address zero are ignored. Sensors Freescale Semiconductor Table 4-5 Initialization Command Structure Address D1 ...
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... CLOSE BUS SWITCH MMA81XXEG SET BF ? FLAG SET BF FLAG WAIT FOR NEXT DSI BUS COMMAND Figure 4-1. Initialization Sequence REVERSE N INITIALIZATION COMMAND AT BUSOUT ENABLE I CURRENT RESP DRIVE AT BUSIN DELAY 10 μs MEASURE BUSIN VOLTAGE N V < BUSIN THH Y CLOSE BUS SWITCH Sensors Freescale Semiconductor ...
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... The data field in the command structure is ignored but is included in the CRC calculation. No action is taken if this command is sent to the DSI Global Device Address. Table 4-4 Read Acceleration Data Command Structure Address Table 4-5 Short Response Structure - Read Acceleration Data Command Response Length D14 D13 8 9 Sensors Freescale Semiconductor Command Response D12 ...
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... D6 D5 AD9 AD8 AD7 AD6 AD5 AD4 Table 4-7 Nominal Sensitivity (10-bit data) Nominal Sensitivity (g/digit) 250 0.61 150 0.366 100 0.244 50 0.122 40 0.0976 20 0.0488 CRC AD3 AD2 AD1 AD0 bits Table 4-5 and Table 4-6. The result is Sensors Freescale Semiconductor D0 ...
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... When a Clear Command is successfully decoded and the address field matches either the assigned device address or the DSI Global Device Address, the bus switch is opened and the device undergoes a full reset operation. There is no response to the Clear Command. Sensors Freescale Semiconductor Command A1 A0 ...
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... The Read Register Data command (described in the full range of customer accessible data. MMA81XXEG 24 Address RD1 RD0 Data RA1 RA0 Data Command CRC bits CRC RD3 RD2 RD1 RD0 bits CRC bits Section 4.6.5) may be used to access Sensors Freescale Semiconductor ...
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... R/W FA2 FA1 FA0 FD3 FD2 4.6.4.1 Format Register Read/Write Control Bit (R/ Write Format Control register selected by FA2 - FA0 0 - Read Format Control register unless global command Sensors Freescale Semiconductor Table 4-15 OTP Field Assignments Bank Select Register DEVCFG1[3: DEVCFG1[7: DEVCFG2[ DEVCFG2[3:0] ...
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... MMA81XXEG 26 Data R/W FA2 FA1 FA0 Table 4-18 Format Control Registers Address Decimal FA2 FA1 FA0 Section 4.6.4.3. CRC FD3 FD2 FD1 FD0 bits Table 4-18 below. The default val- Default Value FD3 FD2 FD1 FD0 Sensors Freescale Semiconductor ...
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... There is no response if the Read Register Data Command is received within a DSI short command structure or if this command is sent to the DSI Global Device Address. The sixteen registers shown in Table 3-1 Table 4-21 Read Register Data Command Address Assignment Sensors Freescale Semiconductor Address ...
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... DSI Global Device Address. Table 4-25 Enable Self-Test Stimulus Command Structure Address MMA81XXEG 28 Command Response D12 D11 D10 Data Command CRC bits AT1 AT0 S GF CRC AT1 AT0 bits CRC bits Sensors Freescale Semiconductor ...
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... Both fields will contain the value PA3 - PA0 to indicate successful device address assignment. Initialization or reverse initialization commands which attempt to assign device address zero are ignored. Sensors Freescale Semiconductor Response D12 D11 ...
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... Unit -0.3 to +40 V -0.3 to +40 V -0.3 to +11 V -0.3 to +3.0 V -0.3 to +3.0 V 400 mA 200 mA ±10 mA ±1400 g ±950 g ±2200 g ±1500 g ±2000 g 1.2 m ±2000 V ±500 V ±200 V -40 to +125 °C -40 to +150 °C J Freescale Semiconductor (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) Sensors ...
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... Device fully characterized at +105 °C and +125 °C. Production units tested +105 °C, with operation at +125 °C guaranteed through correlation with characterization results. 9. Maximum voltage characterized. Minimum voltage tested 100% at final test. Maximum voltage tested 100 final test. Sensors Freescale Semiconductor Symbol Min Typ θ ...
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... V (1) — (3) — 2 mV/mA (3) — — dB (3) μF — — (3) — 700 mΩ (3) Sensors Freescale Semiconductor ...
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... GND Loss Detect (with external 3 kΩ resistor) 92 Measurement Current 93 Detection Resistance 1. Parameters tested 100% at final test. 2. Parameters tested 100% at unit probe. 3. Verified by characterization, not tested in production. 4. (*) Indicates a customer critical characteristic or Freescale important characteristic. 10. The external circuit configuration shown in Sensors Freescale Semiconductor ) ≤ ≤ T ≤ unless otherwise specified. SS ...
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... Sensors Freescale Semiconductor ...
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... UV: UNDERVOLTAGE CONDITION RESUMES GND V CREG V LVR V LVD V LVH LOW-VOLTAGE CONDITION DETECTED POR ASSERTED GND Sensors Freescale Semiconductor UV EXISTS Figure 5-1. V Undervoltage Detection HCAP POR NEGATED Figure 5-2. V Undervoltage Detection CREG POR ASSERTED UV t UVR INTERNAL RESET IS INITIALLY ≥ V ASSERTED UNTIL V CREG ...
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... XXX RESP 1 Figure 5-3. Total Noise Measurement Conditions MMA81XXEG 36 MASTER UUT DOH BUSIN BUSOUT DOL BUSRTN DSI BUS CONFIGURATION COMMAND FORMAT 20 μs CMD 3 CMD 99 RESP 2 RESP 98 MEASUREMENT WINDOW (10910 μs) MEASUREMENT TIMING N CMD 100 XXX RESP 99 RESP 100 Sensors Freescale Semiconductor ...
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... OTP Programming, SPI program control 1. Parameters tested 100% at final test. 2. Parameters tested 100% at unit probe. 3. Verified by characterization, not tested in production. 4. (*) Indicates a customer critical characteristic or Freescale important characteristics. 8. Functionality verified 100% via scan. Timing is directly determined by internal oscillator frequency. Sensors Freescale Semiconductor ) ≤ ≤ T ≤ ...
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... Sensors Freescale Semiconductor ...
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... BUSIN STABILIZATION DSI BUS COMMAND BUSIN D IN Sensors Freescale Semiconductor t t SAMPLE CONVERT t DELAY S/H CONVERSION Figure 5-4. A-to-D Conversion Timing t IFS Figure 5-5. DSI Bus Interframe Timing t CLK CLK GND t D OUT Figure 5-6. Serial Interface Timing t CDIN CDOUT DATA ...
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... CLK. The interface conforms to OUT pin and ADC input are disabled, and the input of the ADC is connected to the C FIL /TEST to exit ADC Test Mode Test mode is entered when the TEST for details of 16-bit SPI packet. FIL Sensors Freescale Semiconductor ...
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... BUSRTN BANDGAP REFERENCE OSCILLATOR SELFTEST TRIM OSC TRIM SELFTEST VOLTAGE C-TO-V g-CELL CONVERTER GAIN TRIM Sensors Freescale Semiconductor REGULATOR REGULATOR LOGIC COMMAND DECODE STATE MACHINE RESPONSE GENERATION SELF-TEST ENABLE A-TO-D CONVERTER LOW-PASS FILTER OFFSET TCS TRIM TRIM Figure A-1. ADC Test Mode Configuration ...
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... Read the OTP memory • Access various internal signals of the MMA81XXEG/MMA82XXEG/MMA82XXTEG in Test mode CLK D OUT GND MMA81XXEG 42 Figure A-2. The corresponding registers may be used to: SERIAL PERIPHERAL REGISTER INTERFACE ARRAY OTP ARRAY Figure A-2. OTP Interface Overview TO DIGITAL INTERFACE Sensors Freescale Semiconductor ...
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... D /V A[5] A[4] A[3] A[2] A[1] A[ OUT Figure A-4. Serial Data Timing, Register Array Read Operation Should the data transfer be corrupted by e.g., noise on the clock line, a device reset is required to restore the state of internal logic. Sensors Freescale Semiconductor BIT ⎯ A[2] A[1] ...
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... SPI_WRITE_ENABLE bit (address $29[5]). This bit may be set by writing the value $0 to address $20. Internal register read and write operations are described in MMA81XXEG D[7] D[6 D[5] D[4] D[3] D[2] D[1] D[0] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Section 3. pin during the 8th through 15th falling OUT Sensors Freescale Semiconductor ...
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... Sensors Freescale Semiconductor PACKAGE DIMENSIONS MMA81XXEG 45 ...
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... MMA81XXEG 46 PACKAGE DIMENSIONS Sensors Freescale Semiconductor ...
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