MMA8205EGR2 Freescale Semiconductor, MMA8205EGR2 Datasheet - Page 37

• Manufacturer Part Number: MMA8205EGR2
• Description: Board Mount Accelerometers X- AXIS 50G SOIC 16
• Manufacturer: Freescale Semiconductor
• Series: MMA82r

Specifications of MMA8205EGR2

• Sensing Axis: X
• Acceleration: 50 g
• Sensitivity: 8.02 mV/g
• Package / Case: SOIC-16
• Axis: X or Y
• Acceleration Range: ±50g
• Voltage - Supply: 6.3 V ~ 30 V
• Output Type: Digital
• Bandwidth: -
• Interface: SPI
• Mounting Type: Surface Mount
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Sensors
Freescale Semiconductor
5.7
V
1. Parameters tested 100% at final test.
2. Parameters tested 100% at unit probe.
3. Verified by characterization, not tested in production.
4. (*) Indicates a customer critical characteristic or Freescale important characteristics.
8. Functionality verified 100% via scan. Timing is directly determined by internal oscillator frequency.
Ref
L
120
121
122
123
124
125 Initialization to Bus Switch Closing
126 Signal Bit Transition Time
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141 Internal Oscillator Frequency
142
143
144 OTP Programming, SPI program control
≤
(V
VHCAP Undervoltage Reset Period
(see
V
Analog to digital converter (see
BUSIN and BUSOUT response current transition
Loss of Signal Reset Time
BUSIN or BUSOUT Timing to Response Current
Interframe Separation Time (see
Low Pass Filter
Ground Loss Detection Filter Time
Reset Recovery Time
Logic Duty Cycle
BUS
HCAP
CONTROL TIMING
Sample time
Conversion time
Delay following bus idle
1.0 mA to 9.0 mA, 9.0 to 1.0 mA
Maximum time below frame threshold
BUSIN or BUSOUT ≤ V
BUSIN or BUSOUT ≤ V
Following Read Write NVM Command
Following Initialization or Reverse Initialization
Following other DSI bus commands
(4-pole, -3 db Rolloff Frequency)
(2-pole, -3 db Rolloff Frequency)
Cycles of f
Time
POR negated to Initialization Command
POR negated to 180 Hz Data Valid
POR negated to 400 Hz Data Valid
Logic ‘0’
Logic ‘1’
- V
Figure
BS = 1
BS = 0
< V
SS
RA
)
5-1)
≤
to POR assertion
OSC
V
H
, V
Characteristic
L
≤
(V
THL
THH
HCAP
to I
to I
Figure
Figure
- V
BUS
BUS
SS
≥ 7 mA
≤ 5 mA
5-4)
)
5-5)
≤
V
H
,T
L
≤
T
A
≤
T
*
*
H
, unless otherwise specified.
t
Symbol
CONVERT
t
t
t
BW
BW
GNDETC
GNDETC
SAMPLE
t
t
t
t
t
t
t
RESET
RESET
RESET
DELAY
PROG
t
RSPH
f
RSPL
D
D
t
t
t
t
t
t
OSC
UVR
t
t
ITR
BIT
TO
IFS
IFS
IFS
IFS
BS
CH
CL
OUT
OUT
0.95
4.28
7.13
2.85
3.80
Min
200
360
162
4.5
89
20
20
10
60
—
—
—
—
—
—
—
—
5
2
16384
4.096
Typ
400
180
1.0
4.5
7.5
3.0
5.3
2.4
4.0
—
—
—
—
—
—
—
—
—
—
—
33
67
—
Max
1.05
4.73
7.88
3.15
4.20
138
200
440
198
100
7.5
3.0
3.0
10
—
—
—
—
—
—
—
40
90
2
MMA81XXEG
mA/μs
cycles
Units
MHz
ms
ms
ms
Hz
Hz
ms
ms
ms
ms
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
%
%
(8)
(8)
(8)
(8)
(3)
(3)
(3)
(8)
(3)
(3)
(3)
(3)
(3)
(3)
(1)
(1)
(8)
(8)
(8)
(3)
(3)
(1)
(8)
(8)
(8)
37