MMA8205EGR2 Freescale Semiconductor, MMA8205EGR2 Datasheet - Page 5

• Manufacturer Part Number: MMA8205EGR2
• Description: Board Mount Accelerometers X- AXIS 50G SOIC 16
• Manufacturer: Freescale Semiconductor
• Series: MMA82r

Specifications of MMA8205EGR2

• Sensing Axis: X
• Acceleration: 50 g
• Sensitivity: 8.02 mV/g
• Package / Case: SOIC-16
• Axis: X or Y
• Acceleration Range: ±50g
• Voltage - Supply: 6.3 V ~ 30 V
• Output Type: Digital
• Bandwidth: -
• Interface: SPI
• Mounting Type: Surface Mount
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Sensors
Freescale Semiconductor
1.3
The following paragraphs provide descriptions of the general function of each pin.
1.3.1
Power is supplied to the ASIC through BUSIN or BUSOUT and BUSRTN. The supply voltage is rectified internally and applied
to the H
supply return node. All V
connected to the BUSRTN node on the PWB. To ensure stability of the internal voltage regulator and meet DFMEA requirements,
the connection from H
printed wiring assembly.
The voltage on H
a short word Read Acceleration Data command, and report the undervoltage condition by setting the Undervoltage (U) flag.
Should the undervoltage condition persist for more than one millisecond, the internal Power-On Reset (POR) circuit is activated
and the device will not respond until the voltage at H
initialization.
1.3.2
The BUSIN pin is normally connected to the DSI bus and supports bidirectional communication with the master.
The MMA81XXEG, MMA82XXEG and MMA82XXTEG supports reverse initialization for improved system fault tolerance. In the
event that the DSI bus cannot support communication between the master and BUSIN pin, communication with the master may
be conducted via the BUSOUT pin and the BUSIN pin can be used to access other DSI devices.
1.3.3
The BUSOUT pin is normally connected to the DSI bus for daisy-chained bus configurations. In support of fault tolerance at the
system level, the BUSOUT pin can be used as an input for reverse initialization and data communication.
The internal bus switch is always open following reset. The bus switch is closed when data bit D6 is set when an Initialization or
Reverse Initialization command is received.
1.3.4
This pin provides the common return for power and signalling.
1.3.5
The internal voltage regulator requires external capacitance to the V
without excessive internal resistance or inductance. An optional electrolytic capacitor may be required if a longer power down
delay is required.
Figure 1-3
provided for redundancy. It is recommended that both C
reliability.
CAP
PIN FUNCTIONS
H
BUSIN
BUSOUT
BUSRTN
C
illustrates the relationship between capacitance, series resistance and voltage regulator stability. Two C
pin. An external capacitor connected to HCAP forms the positive supply for the integrated voltage regulator. V
CAP
REG
CAP
and V
is monitored. If the voltage falls below a specified level, the device will return the value zero in response to
CAP
SS
SS
to the external capacitor should be as short as possible and should not be routed elsewhere on the
pins are internally connected to BUSRTN. To obtain specified performance, all V
Figure 1-3. Voltage Regulator Capacitance and Series Resistance
ESR
700 mΩ
0
STABLE, UNACCEPTABLE
NOISE PERFORMANCE
1 μF
CAP
is restored to operating levels and the device has undergone post-reset
REG
pins are connected to the external capacitor(s) for best system
STABLE
C
REG
SS
pin for stability. This should be a high grade capacitor
100 μF
SS
nodes should be
MMA81XXEG
REG
pins are
SS
is
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