ADAU1361BCPZ Analog Devices Inc, ADAU1361BCPZ Datasheet - Page 42

• Manufacturer Part Number: ADAU1361BCPZ
• Description: IC CODEC 24B PLL 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: Audio Codecr

Specifications of ADAU1361BCPZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• Voltage - Supply, Analog: 1.8 V ~ 3.6 V
• Voltage - Supply, Digital: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN, CSP Exposed Pad
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 7
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 101dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADAU1361
SERIAL DATA INPUT/OUTPUT PORTS
The flexible serial data input and output ports of the ADAU1361
can be set to accept or transmit data in 2-channel format or in a
4-channel TDM stream to interface to external ADCs or DACs.
Data is processed in twos complement, MSB first format. The
left channel data field always precedes the right channel data
field in 2-channel streams. In TDM mode, Slot 0 and Slot 1 are
in the first half of the audio frame, and Slot 2 and Slot 3 are in
the second half of the frame. The serial modes and the position
of the data in the frame are set in Register R15 to Register R18
(serial port and converter control registers, Address 0x4015 to
Address 0x4018).
If the PLL of the ADAU1361 is not used, the serial data clocks
must be synchronous with the ADAU1361 master clock input.
The LRCLK and BCLK pins are used to clock both the serial
input and output ports. The ADAU1361 can be set as the master
or the slave in a system. Because there is only one set of serial
data clocks, the input and output ports must always be both
master or both slave.
Register R15 and Register R16 (serial port control registers,
Address 0x4015 and Address 0x4016) allow control of clock
polarity and data input modes. The valid data formats are I
left-justified, right-justified (24-/20-/18-/16-bit), and TDM. In
all modes except for the right-justified modes, the serial port
inputs an arbitrary number of bits up to a limit of 24. Extra bits
do not cause an error, but they are truncated internally.
Table 25. Data Format Configurations
Format
I
Left-Justified (see
Right-Justified
TDM with Clock
TDM with Pulse
2
S
(see Figure 57)
Figure 58)
(see Figure 59)
(see Figure 60)
(see Figure 61)
LRCLK Polarity (LRPOL)
Frame begins on falling edge
Frame begins on rising edge
Frame begins on rising edge
Frame begins on falling edge
Frame begins on rising edge
LRCLK Mode
(LRMOD)
50% duty cycle
50% duty cycle
50% duty cycle
50% duty cycle
Pulse
2
S,
Rev. C | Page 42 of 80
BCLK Polarity
(BPOL)
Data changes
on falling edge
Data changes
on falling edge
Data changes
on falling edge
Data changes
on falling edge
Data changes
on falling edge
The serial port can operate with an arbitrary number of BCLK
transitions in each LRCLK frame. The LRCLK in TDM mode
can be input to the ADAU1361 either as a 50% duty cycle clock
or as a bit-wide pulse.
When the LRCLK is set as a pulse, a 47 pF capacitor should be
connected between the LRCLK pin and ground (see Figure 56).
This capacitor is necessary in both master and slave modes to
properly align the LRCLK signal to the serial data stream.
In TDM mode, the ADAU1361 can be a master for f
48 kHz. Table 24 lists the modes in which the serial output
port can function.
Table 24. Serial Output Port Master/Slave Mode Capabilities
f
48 kHz
96 kHz
Table 25 describes the proper configurations for standard audio
data formats.
S
Figure 56. LRCLK Capacitor Alignment, TDM Pulse Mode
2-Channel Modes (I
Justified, Right-Justified)
Master and slave
Master and slave
BCLK Cycles/Audio
Frame (BPF[2:0])
32 to 64
32 to 64
32 to 64
64 to 128
64 to 128
47pF
ADAU1361
LRCLK
BCLK
2
S, Left-
Data Delay from LRCLK
Edge (LRDEL[1:0])
Delayed from LRCLK edge
by 1 BCLK
Aligned with LRCLK edge
Delayed from LRCLK edge
by 8 or 16 BCLKs
Delayed from start of word
clock by 1 BCLK
Delayed from start of word
clock by 1 BCLK
4-Channel TDM
Master and slave
Slave
S
up to