ADAU1361BCPZ Analog Devices Inc, ADAU1361BCPZ Datasheet - Page 47

IC CODEC 24B PLL 32LFCSP

ADAU1361BCPZ

Manufacturer Part Number
ADAU1361BCPZ
Description
IC CODEC 24B PLL 32LFCSP
Manufacturer
Analog Devices Inc
Type
Audio Codecr
Datasheet

Specifications of ADAU1361BCPZ

Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
2 / 2
Sigma Delta
No
Voltage - Supply, Analog
1.8 V ~ 3.6 V
Voltage - Supply, Digital
1.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-VFQFN, CSP Exposed Pad
Audio Codec Type
Stereo
No. Of Adcs
2
No. Of Dacs
2
No. Of Input Channels
6
No. Of Output Channels
7
Adc / Dac Resolution
24bit
Adcs / Dacs Signal To Noise Ratio
101dB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADAU1361BCPZ
Manufacturer:
TOSHIBA
Quantity:
1 650
Part Number:
ADAU1361BCPZ
Manufacturer:
ADI
Quantity:
624
Part Number:
ADAU1361BCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
ADAU1361BCPZ-R7
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Byte
4
4
4
5
5
R2: Digital Microphone/Jack Detection Control, 16,392 (0x4008)
Bit 7
Table 29. Digital Microphone/Jack Detection Control Register
Bits
[7:6]
[5:4]
0
Bits
[6:3]
[2:1]
0
1
0
Bit Name
JDDB[1:0]
JDFUNC[1:0]
JDPOL
JDDB[1:0]
Bit 6
Bit Name
R[3:0]
X[1:0]
Type
Lock
PLLEN
Description
Jack detect debounce time.
JACKDET/MICIN pin function. Enables or disables the jack detect function or configures the pin for a digital
microphone input.
Jack detect polarity. Detects high or low signal.
0 = detect high signal (default).
1 = detect low signal.
Setting
00
01
10
11
Setting
00
01
10
11
Bit 5
Description
PLL integer setting.
Setting
0010
0011
0100
0101
0110
0111
1000
PLL input clock divider.
Setting
00
01
10
11
Type of PLL. When set to integer mode, the values of M and N are ignored.
0 = integer (default).
1 = fractional.
PLL lock. This read-only bit is flagged when the PLL has finished locking.
0 = PLL unlocked (default).
1 = PLL locked.
PLL enable.
0 = PLL disabled (default).
1 = PLL enabled.
JDFUNC[1:0]
Bit 4
Rev. C | Page 47 of 80
Debounce Time
5 ms (default)
10 ms
20 ms
40 ms
Pin Function
Jack detect off (default)
Jack detect on
Digital microphone input
Reserved
Value of R
2 (default)
3
4
5
6
7
8
Value of X
1 (default)
2
3
4
Bit 3
Bit 2
Reserved
Bit 1
ADAU1361
Bit 0
JDPOL

Related parts for ADAU1361BCPZ