ADAU1361BCPZ Analog Devices Inc, ADAU1361BCPZ Datasheet - Page 58

IC CODEC 24B PLL 32LFCSP

ADAU1361BCPZ

Manufacturer Part Number
ADAU1361BCPZ
Description
IC CODEC 24B PLL 32LFCSP
Manufacturer
Analog Devices Inc
Type
Audio Codecr
Datasheet

Specifications of ADAU1361BCPZ

Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
2 / 2
Sigma Delta
No
Voltage - Supply, Analog
1.8 V ~ 3.6 V
Voltage - Supply, Digital
1.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-VFQFN, CSP Exposed Pad
Audio Codec Type
Stereo
No. Of Adcs
2
No. Of Dacs
2
No. Of Input Channels
6
No. Of Output Channels
7
Adc / Dac Resolution
24bit
Adcs / Dacs Signal To Noise Ratio
101dB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADAU1361BCPZ
Manufacturer:
TOSHIBA
Quantity:
1 650
Part Number:
ADAU1361BCPZ
Manufacturer:
ADI
Quantity:
624
Part Number:
ADAU1361BCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
ADAU1361BCPZ-R7
Manufacturer:
ADI/亚德诺
Quantity:
20 000
ADAU1361
R16: Serial Port Control 1, 16,406 (0x4016)
Bit 7
Table 43. Serial Port Control 1 Register
Bits
[7:5]
4
3
2
[1:0]
Bit Name
BPF[2:0]
ADTDM
DATDM
MSBP
LRDEL[1:0]
Bit 6
BPF[2:0]
Number of bit clock cycles per LRCLK audio frame.
Data delay from LRCLK edge (in BCLK units).
Description
Setting
000
001
010
011
100
101
110
111
ADC serial audio data channel position in TDM mode.
0 = left first (default).
1 = right first.
DAC serial audio data channel position in TDM mode.
0 = left first (default).
1 = right first.
MSB position in the LRCLK frame.
0 = MSB first (default).
1 = LSB first.
Setting
00
01
10
11
Bit 5
Bit 4
ADTDM
Bit Clock Cycles
64 (default)
32
48
128
Reserved
Reserved
Reserved
Reserved
Delay (Bit Clock Cycles)
1 (default)
0
8
16
Rev. C | Page 58 of 80
Bit 3
DATDM
Bit 2
MSBP
Bit 1
LRDEL[1:0]
Bit 0

Related parts for ADAU1361BCPZ