ADAV801ASTZ Analog Devices Inc, ADAV801ASTZ Datasheet - Page 25

• Manufacturer Part Number: ADAV801ASTZ
• Description: IC CODEC AUDIO R-DVD 3.3V 64LQFP
• Manufacturer: Analog Devices Inc
• Type: Audio Codecr

Specifications of ADAV801ASTZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 102 / 101
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 2
• No. Of Output Channels: 2
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 102dB
• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: LQFP
• Adc/dac Resolution: 24b
• Interface Type: Serial (SPI)
• Mounting: Surface Mount
• Number Of Adc's: 2
• Number Of Dac's: 2
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 64
• Power Supply Type: Analog/Digital
• Sample Rate: 96KSPS
• Screening Level: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADAV801EBZ - BOARD EVALUATION FOR ADAV801
• Lead Free Status / Rohs Status: Compliant

Table 10. Professional Audio Standard
Address
N
N + 1
N + 2
N + 3
N + 4
N + 5
N + 6
N + 7
N + 8
N + 9
N + 10
N + 11
N + 12
N + 13
N + 14
N + 15
N + 16
N + 17
N + 18
N + 19
N + 20
N + 21
N + 22
N + 23
1
The standards allow the channel status bits in each subframe to
be independent, but ordinarily the channel status bits in the two
subframes of each frame are the same. The channel status bits
are defined differently for the consumer audio standards and
the professional audio standards. The 192 channel status bits are
organized into 24 bytes and have the interpretations shown in
Table 9 and Table 10.
The S/PDIF transmitter and receiver have a comprehensive
register set. The registers give the user full access to the
functions of the S/PDIF block, such as detecting nonaudio and
validity bits, Q subcodes, and preambles. The channel status bits
as defined by the IEC60958 and AES3 specifications are stored
in register buffers for ease of use. An autobuffering function
allows channel status bits and user bits read by the receiver to be
copied directly to the transmitter block, removing the need for
user intervention.
Receiver Section
The ADAV801 uses a double-buffering scheme to handle read-
ing channel status and user bit information. The channel status
N = 0x20 for receiver channel status buffer.
N = 0x38 for transmitter channel status buffer.
1
7
f
Scaling
Alignment
Frequency
S
User Bit Management
Alphanumeric Channel Destination Data—First Character
Alphanumeric Channel Destination Data—Last Character
Sample
Level
Alphanumeric Channel Origin Data—First Character
Alphanumeric Channel Origin Data—Last Character
Reliability Flags
Cyclic Redundancy Check Character (CRCC)
Alphanumeric Channel Destination Data
Alphanumeric Channel Destination Data
6
Frequency (f
Local Sample Address Code—MSW
Alphanumeric Channel Origin Data
Alphanumeric Channel Origin Data
Local Sample Address Code—LSW
5
Lock
Source Word
Sample
Local Sample Address Code
Local Sample Address Code
Time of Day Code—MSW
Length
Time of Day Code—LSW
Channel Identification
Time of Day Code
Time of Day Code
4
S
Data Bits
)
Reserved
Emphasis
3
2
Reserved
Use of Auxiliary Mode
Channel Mode
Reserved
Sample Bits
1
Non-
Audio
Digital Audio
Reference
Signal
0
Pro/Con
= 1
Rev. A | Page 25 of 60
bits are available as a memory buffer, taking up 24 consecutive
register locations. The user bits are read using an indirect
memory addressing scheme, where the receiver user bit
indirect-address register is programmed with an offset to the
user bit buffer, and the receiver user bit data register can be read
to determine the user bits at that location. Reading the receiver
user bit data register automatically updates the indirect address
register to the next location in the buffer. Typically, the receiver
user bit indirect-address register is programmed to zero (the
start of the buffer), and the receiver user bit data register is read
repeatedly until all the buffer’s data has been read. Figure 46
and Figure 47 show how receiving the channel status bits and
user bits is implemented.
The S/PDIF receive buffer is updated continuously by the
incoming S/PDIF stream. Once all the channel status bits for
the block (192 for Channel A and 192 for Channel B) are
received, the bits are copied into the receiver channel status
buffer. This buffer stores all 384 bits of channel status
information, and the RxCSSWITCH bit in the channel status
switch buffer register determines whether the Channel A or the
Channel B status bits are required to be read. The receive
channel status bit buffer is 24 bytes long and spans the address
range from 0x20 to 0x37.
Because the channel status bits of an S/PDIF stream rarely
change, a software interrupt/flag bit, RxCSBINT, is provided to
notify the host control either that a new block of channel status
bits is available or that the first five bytes of channel status
information have changed from a previous block. The function
of the RxCSBINT is controlled by the RxBCONF3 bit in the
Receiver Buffer Configuration register.
BUFFER
S/PDIF
16...23
FIRST
8...15
0...7
FIRST BUFFER
RECEIVE
BUFFER
DIRIN
S/PDIF
Figure 47. Receiver User Bit Buffer
Figure 46. Channel Status Buffer
USER-BIT
BUFFER
16...23
8...15
0...7
(24 × 8 BITS)
(24 × 8 BITS)
CHANNEL
STATUS A
CHANNEL
STATUS B
ADDRESS = 0x50
ADDRESS = 0x51
RECEIVER USER BIT
RECEIVER USER BIT
INDIRECT ADDRESS
DATA REGISTER
SECOND BUFFER
(0x20 TO 0x37)
RxCSSWITCH
REGISTER
CS BUFFER
RECEIVE
ADAV801